Update for new pac

Cargo.toml

@@ -32,7 +32,7 @@ embedded-hal = { version = "0.2.6", features = ["unproven"] }
 embedded-dma = "0.2.0"
 cortex-m = { version = "^0.7.7", features = ["critical-section-single-core"] }
 defmt = { version = ">=0.2.0,<0.4", optional = true }
-stm32h7 = { version = "^0.15.1", default-features = false }
+stm32h7 = { version = "0.16.0", package = "stm32h7-staging", features = ["critical-section"], default-features = false }
 void = { version = "1.0.2", default-features = false }
 cast = { version = "0.3.0", default-features = false }
 nb = "1.0.0"

examples/display-dsi-command-teartest-stm32h747i-disco.rs

@@ -34,7 +34,7 @@ use cortex_m_rt::{entry, exception};
 use crate::utilities_display::display_target::BufferedDisplay;
 use stm32h7xx_hal::gpio::Speed;
 use stm32h7xx_hal::ltdc;
-use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL_A;
+use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL;
 use stm32h7xx_hal::{prelude::*, stm32};
 
 use embedded_display_controller::DisplayController;
@@ -186,7 +186,7 @@ fn main() -> ! {
         gpioh.ph5               // SDNWE
     };
 
-    let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL_A::Pll2R);
+    let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL::Pll2R);
     // TODO: incorrect for disco!
     let sdram_chip = stm32_fmc::devices::is42s32800g_6::Is42s32800g {};
     let mut sdram = dp.FMC.sdram(

examples/display-dsi-video-stm32h747i-disco.rs

@@ -29,7 +29,7 @@ use cortex_m_rt::{entry, exception};
 use crate::utilities_display::display_target::BufferedDisplay;
 use stm32h7xx_hal::gpio::Speed;
 use stm32h7xx_hal::ltdc;
-use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL_A;
+use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL;
 use stm32h7xx_hal::{prelude::*, rtc, stm32};
 
 use embedded_display_controller::DisplayController;
@@ -188,7 +188,7 @@ fn main() -> ! {
         gpioh.ph5               // SDNWE
     };
 
-    let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL_A::Pll2R);
+    let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL::Pll2R);
     // TODO: incorrect for disco!
     let sdram_chip = stm32_fmc::devices::is42s32800g_6::Is42s32800g {};
     let mut sdram = dp.FMC.sdram(

examples/display-dsi-video-teartest-stm32h747i-disco.rs

@@ -33,7 +33,7 @@ use cortex_m_rt::{entry, exception};
 use crate::utilities_display::display_target::BufferedDisplay;
 use stm32h7xx_hal::gpio::Speed;
 use stm32h7xx_hal::ltdc;
-use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL_A;
+use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL;
 use stm32h7xx_hal::{prelude::*, stm32};
 
 use embedded_display_controller::DisplayController;
@@ -185,7 +185,7 @@ fn main() -> ! {
         gpioh.ph5               // SDNWE
     };
 
-    let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL_A::Pll2R);
+    let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL::Pll2R);
     // TODO: incorrect for disco!
     let sdram_chip = stm32_fmc::devices::is42s32800g_6::Is42s32800g {};
     let mut sdram = dp.FMC.sdram(

examples/ethernet-nucleo-h743zi2.rs

@@ -69,7 +69,7 @@ fn main() -> ! {
 
     // Initialise SRAM3
     info!("Setup RCC...                  ");
-    dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
+    dp.RCC.ahb2enr().modify(|_, w| w.sram3en().set_bit());
 
     // Initialise clocks...
     let rcc = dp.RCC.constrain();

examples/ethernet-rtic-stm32h747i-disco.rs

@@ -127,7 +127,10 @@ mod app {
         let pwrcfg = pwr.smps().freeze();
 
         // Link the SRAM3 power state to CPU1
-        ctx.device.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
+        ctx.device
+            .RCC
+            .ahb2enr()
+            .modify(|_, w| w.sram3en().set_bit());
 
         // Initialise clocks...
         let rcc = ctx.device.RCC.constrain();

examples/ethernet-stm32h747i-disco.rs

@@ -46,7 +46,7 @@ fn main() -> ! {
 
     // Link the SRAM3 power state to CPU1
     info!("Setup RCC...                  ");
-    dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
+    dp.RCC.ahb2enr().modify(|_, w| w.sram3en().set_bit());
 
     // Initialise clocks...
     let rcc = dp.RCC.constrain();

examples/i2c4_bdma.rs

@@ -36,10 +36,12 @@ fn main() -> ! {
     let dp = pac::Peripherals::take().expect("Cannot take peripherals");
 
     // Run D3 / SRD domain
-    #[cfg(not(feature = "rm0455"))]
-    dp.PWR.cpucr.modify(|_, w| w.run_d3().set_bit());
+    #[cfg(not(any(feature = "rm0455", feature = "rm0399")))]
+    dp.PWR.cpucr().modify(|_, w| w.run_d3().set_bit());
+    #[cfg(feature = "rm0399")]
+    dp.PWR.cpu1cr().modify(|_, w| w.run_d3().set_bit());
     #[cfg(feature = "rm0455")]
-    dp.PWR.cpucr.modify(|_, w| w.run_srd().set_bit());
+    dp.PWR.cpucr().modify(|_, w| w.run_srd().set_bit());
 
     let pwr = dp.PWR.constrain();
     let pwrcfg = example_power!(pwr).freeze();

examples/qspi_mdma.rs

@@ -70,9 +70,7 @@ fn main() -> ! {
     );
     qspi.configure_mode(QspiMode::FourBit).unwrap();
     // Disable address phase
-    qspi.inner_mut()
-        .ccr
-        .modify(|_, w| unsafe { w.admode().bits(0) });
+    qspi.inner_mut().ccr().modify(|_, w| w.admode().set(0));
 
     // Source buffer in TCM
     let mut source_buffer: [u8; 80] = [0x4A; 80];

examples/rtic_low_power.rs

@@ -56,10 +56,12 @@ mod app {
         let mut syscfg = ctx.device.SYSCFG;
 
         // Run D3 / SRD domain
-        #[cfg(not(feature = "rm0455"))]
-        ctx.device.PWR.cpucr.modify(|_, w| w.run_d3().set_bit());
+        #[cfg(not(any(feature = "rm0455", feature = "rm0399")))]
+        ctx.device.PWR.cpucr().modify(|_, w| w.run_d3().set_bit());
+        #[cfg(feature = "rm0399")]
+        ctx.device.PWR.cpu1cr().modify(|_, w| w.run_d3().set_bit());
         #[cfg(feature = "rm0455")] // 7b3/7a3/7b0 parts
-        ctx.device.PWR.cpucr.modify(|_, w| w.run_srd().set_bit());
+        ctx.device.PWR.cpucr().modify(|_, w| w.run_srd().set_bit());
 
         let pwr = ctx.device.PWR.constrain();
         let vos = example_power!(pwr).freeze();

examples/sai_dma_passthru.rs

@@ -194,7 +194,7 @@ fn main() -> ! {
 
         // wait until sai1's fifo starts to receive data
         info!("sai1 fifo waiting to receive data");
-        while sai1_rb.cha().sr.read().flvl().is_empty() {}
+        while sai1_rb.cha().sr().read().flvl().is_empty() {}
         info!("audio started");
 
         sai1.enable();

examples/spi-dma-rtic.rs

@@ -147,7 +147,7 @@ mod app {
             transfer.pause(|spi| {
                 // At this point, the DMA transfer is done, but the data is still in the SPI output
                 // FIFO. Wait for it to complete before disabling CS.
-                while spi.inner().sr.read().txc().bit_is_clear() {}
+                while spi.inner().sr().read().txc().bit_is_clear() {}
                 cs.set_high();
             });
         });
@@ -163,8 +163,8 @@ mod app {
 
                 // Enable TX DMA support, enable the SPI peripheral, and start the transaction.
                 spi.enable_dma_tx();
-                spi.inner_mut().cr1.modify(|_, w| w.spe().enabled());
-                spi.inner_mut().cr1.modify(|_, w| w.cstart().started());
+                spi.inner_mut().cr1().modify(|_, w| w.spe().enabled());
+                spi.inner_mut().cr1().modify(|_, w| w.cstart().started());
 
                 // The transaction immediately begins as the TX FIFO is now being filled by DMA.
             });

examples/spi-dma.rs

@@ -131,11 +131,11 @@ fn main() -> ! {
 
         // Enable the SPI by setting the SPE bit
         spi.inner_mut()
-            .cr1
+            .cr1()
             .write(|w| w.ssi().slave_not_selected().spe().enabled());
 
         // write CSTART to start a transaction in master mode
-        spi.inner_mut().cr1.modify(|_, w| w.cstart().started());
+        spi.inner_mut().cr1().modify(|_, w| w.cstart().started());
     });
 
     // Wait for transfer to complete
@@ -171,7 +171,7 @@ fn main() -> ! {
     transfer.pause(|spi| {
         // At this point, the DMA transfer is done, but the data is still in the
         // SPI output FIFO. Wait for it to complete
-        while spi.inner().sr.read().txc().bit_is_clear() {}
+        while spi.inner().sr().read().txc().bit_is_clear() {}
     });
 
     info!("Chunked transfer complete!");