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Add decoder for RVV instructions #501

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@howjmay howjmay commented Oct 17, 2024

relate to #504

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Benchmarks

Benchmark suite Current: f092a89 Previous: 9225e3b Ratio
Dhrystone 1473 Average DMIPS over 10 runs 1550 Average DMIPS over 10 runs 1.05
Coremark 1416.118 Average iterations/sec over 10 runs 1409.498 Average iterations/sec over 10 runs 1.00

This comment was automatically generated by workflow using github-action-benchmark.

@howjmay howjmay force-pushed the rvv branch 2 times, most recently from 7de4a2a to 11ea214 Compare October 18, 2024 00:35
@howjmay howjmay changed the title Support RVV instructions Add decoder for RVV instructions Oct 18, 2024
@howjmay howjmay force-pushed the rvv branch 5 times, most recently from 2dcaaf6 to 73db290 Compare October 20, 2024 14:52
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jserv commented Oct 20, 2024

How can you test the RVV instructions?

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howjmay commented Oct 20, 2024

A test set own by chipsalliance is here. https://github.com/chipsalliance/riscv-vector-tests/tree/main

I think we can test instructions' behavior with this repo. However, testing decoder is harder. I think I will Spike the verify the behavior, or generating the test cases

@@ -370,6 +370,9 @@ static bool has_loops = false;
}

#include "rv32_template.c"
#if RV32_HAS(EXT_RVV)
#include "rv32_rvv_template.c"
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Rename it to rv32_vector.c

Comment on lines +5 to +9
/*
* This file is auto-generated by running 'make' in
* https://github.com/riscv/riscv-opcodes (9226b0d)
* and it is temporarily used by RVV only
*/
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Related: #103

Do you think it makes sense to replace the existing hand-written RISC-V instruction decoder with the generated one?

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I think the current one is good for education, especially the comments are valuable.
However I think having a table to clearly store the instructions in human-readable form is good for the future development.

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But this encoding.h is only a temporary header file for me to decode rvv instructions.

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2 participants