#

chisel

Here are 157 public repositories matching this topic...

OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor

chisel risc-v microarchitecture

Updated Dec 23, 2024
Scala

chisel

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

Updated Dec 23, 2024
Scala

chipsalliance / rocket-chip

Rocket Chip Generator

scala rocket-chip chip-generator chisel riscv rtl

Updated Dec 3, 2024
Scala

riscv-boom / riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

scala berkeley boom rocket-chip chisel riscv rtl riscv-boom

Updated Oct 1, 2024
Scala

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha

Updated Dec 23, 2024
Scala

ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

chisel riscv rtl

Updated Aug 9, 2024
Scala

RadicalCSG / Chisel.Prototype

Work in progress prototype for the Chisel Level Editor, for Unity

prototype unity mapping realtime chisel csg level-editor bsp leveldesign level-design constructive-solid-geometry

Updated Oct 5, 2024
C#

m3rcer / Chisel-Strike

A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.

socks5 chisel cobalt-strike aggressor-scripts redteaming

Updated Mar 25, 2024
C#

T-K-233 / RISC-V-Single-Cycle-CPU

RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

chisel verilog logisim risc-v

Updated Jul 24, 2024
Verilog

opiran-club / pf-tun

All-in-one OPIran scripts

iptables optimizer chisel frp socat tunneling ssh-tunnel softether tunnelbroker 6to4 private-ip bbrv3

Updated Jul 18, 2024
Shell

Azumi67 / Chisel_multipleServers

Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.

tunnel openvpn tcp udp chisel v2ray reverse-tunnel wireguard azumi

Updated Jun 17, 2024
Python

ucb-bar / chiseltest

The batteries-included testing and formal verification library for Chisel-based RTL designs.

testing verification chisel formal

Updated Aug 19, 2024
Scala

bu-icsg / dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

neural-network hardware rocket-chip chisel riscv rtl rocc

Updated Jan 23, 2020
Scala

alanjian85 / raster-i

A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.

fpga gpu chisel rasterizer tiled-deferred vitis-hls

Updated Nov 24, 2024
C++

t3l3machus / pentest-pivoting

A compact guide to network pivoting for penetration testings / CTF challenges.

ssh network proxy hacking socks5 chisel pentesting proxychains socks4 sshuttle burpsuite pivoting double-pivoting

Updated Jul 19, 2024

ucb-bar / constellation

A Chisel RTL generator for network-on-chip interconnects

hardware chisel rtl soc noc interconnect network-on-chip

Updated Nov 19, 2024
Scala

MaxXSoft / Fuxi

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

scala cpu fpga chisel riscv

Updated Jun 28, 2021
Verilog

fomu-workshop

im-tomu / fomu-workshop

Support files for participating in a Fomu workshop

fpga vhdl chisel riscv verilog hdl litex migen fomu fomu-workshop

Updated Mar 17, 2024
Verilog

ucsc-vama / essent

high-performance RTL simulator

scala chisel rtl firrtl

Updated Jun 19, 2024
Scala

chiselverify / chiselverify

A dynamic verification library for Chisel.

testing coverage scala verification chisel constrained-random-verification functional-coverage bus-functional-model chisel-test timed-assertions

Updated Nov 9, 2024
Scala

Improve this page

Add a description, image, and links to the chisel topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the chisel topic, visit your repo's landing page and select "manage topics."