Pass elaboration args to verilator

trosenkranz · Dec 10, 2023 · 97c5eca · 97c5eca
1 parent 388f4cc
commit 97c5eca
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Showing 2 changed files with 14 additions and 1 deletion.
diff --git a/bin/runSVUnit b/bin/runSVUnit
@@ -172,7 +172,7 @@ if ($simulator eq "modelsim" or $simulator eq "riviera") {
   $cmd .= "-f $vhdlfile " if $vhdlfile;
 } elsif ($simulator eq "verilator") {
   $cmd .= "verilator --binary --top-module testrunner";
-  $cmd .= qq! @compileargs!;
+  $cmd .= qq! @compileargs @elabargs!;
 } elsif ($simulator eq "xsim") {
   $cmd .= "xvhdl -f $vhdlfile && " if $vhdlfile;
   $cmd .= "xvlog --sv --log $vlogfile ";

diff --git a/test/test_frmwrk.py b/test/test_frmwrk.py
@@ -698,3 +698,16 @@ def test_questasim_can_handle_no_elab_args(tmpdir, monkeypatch):
         subprocess.check_call(['runSVUnit'])
 
         assert '-voptargs' not in pathlib.Path('fake_vsim.log').read_text()
+
+
+def test_verilator_can_take_elab_args(tmpdir, monkeypatch):
+    with tmpdir.as_cwd():
+        fake_tool('verilator', log_name_is_tool_name=True)
+
+        monkeypatch.setenv('PATH', get_path_without_sims())
+        monkeypatch.setenv('PATH', '.', prepend=os.pathsep)
+
+        pathlib.Path('dummy_unit_test.sv').write_text('dummy')
+        subprocess.check_call(['runSVUnit', '-e_arg', 'some-arg'])
+
+        assert 'some-arg' in pathlib.Path('fake_verilator.log').read_text()