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add alias for streams/streamlet ports.
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@twoentartian
twoentartian committed Jun 14, 2024
1 parent 8500b4b commit a9e01d5
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Showing 5 changed files with 33 additions and 20 deletions.
2 changes: 1 addition & 1 deletion tydi-lang-json-generator/src/json_representation_all.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@ pub fn translate_from_tydi_project(tydi_project: Arc<RwLock<Project>>, target_va

match &var_value {
tydi_memory_representation::TypedValue::LogicTypeValue(_) => {
let (_, mut type_dependencies, alias_info) = LogicType::translate_from_tydi_project(tydi_project.clone(), target_var.clone())?;
let (_, mut type_dependencies) = LogicType::translate_from_tydi_project(tydi_project.clone(), target_var.clone())?;
output_json_representation.logic_types.append(&mut type_dependencies);
output_json_representation_item_type = JsonRepresentation_item_type::LogicType(target_var_name); //dirty way, will it cause bug in the future?
},
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31 changes: 17 additions & 14 deletions tydi-lang-json-generator/src/json_representation_logic_type.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -166,17 +166,16 @@ impl serde::Serialize for LogicType {
}

impl LogicType {
pub fn translate_from_tydi_project(tydi_project: Arc<RwLock<Project>>, target_var: Arc<RwLock<tydi_memory_representation::Variable>>) -> Result<(Vec<LogicType>, BTreeMap<String, Arc<RwLock<LogicType>>>, Vec<Info>), String> {
pub fn translate_from_tydi_project(tydi_project: Arc<RwLock<Project>>, target_var: Arc<RwLock<tydi_memory_representation::Variable>>) -> Result<(Vec<LogicType>, BTreeMap<String, Arc<RwLock<LogicType>>>), String> {
let target_var_name = name_conversion::get_global_variable_name(target_var.clone());
let var_value = target_var.read().unwrap().get_value();

return Self::translate_from_tydi_project_type_value(tydi_project.clone(), &var_value, target_var_name, Some(target_var.clone()));
}

pub fn translate_from_tydi_project_type_value(tydi_project: Arc<RwLock<Project>>, target_type_value: &tydi_memory_representation::TypedValue, default_var_name: String, raw_var: Option<Arc<RwLock<tydi_memory_representation::Variable>>>) -> Result<(Vec<LogicType>, BTreeMap<String, Arc<RwLock<LogicType>>>, Vec<Info>), String> {
pub fn translate_from_tydi_project_type_value(tydi_project: Arc<RwLock<Project>>, target_type_value: &tydi_memory_representation::TypedValue, default_var_name: String, raw_var: Option<Arc<RwLock<tydi_memory_representation::Variable>>>) -> Result<(Vec<LogicType>, BTreeMap<String, Arc<RwLock<LogicType>>>), String> {
let mut output_dependency = BTreeMap::new();
let mut target_var_name = default_var_name;
let mut output_info: Vec<Info> = vec![];

let mut output_types = vec![];

Expand All @@ -195,7 +194,7 @@ impl LogicType {
if results.is_err() {
return Err(results.err().unwrap());
}
let (mut output_type, mut dependencies, alias_info) = results.ok().unwrap();
let (mut output_type, mut dependencies) = results.ok().unwrap();
output_dependency.append(&mut dependencies);

assert!(output_type.len() > 0);
Expand Down Expand Up @@ -238,7 +237,7 @@ impl LogicType {
_ => unreachable!("{} is not a logic type", target_type_value.get_brief_info()),
}

return Ok((output_types, output_dependency, output_info));
return Ok((output_types, output_dependency));
}

fn translate_single_basic_logic_type(tydi_project: Arc<RwLock<Project>>, target_type: Arc<RwLock<tydi_memory_representation::LogicType>>, target_var_name: &mut String) -> Result<(LogicType, BTreeMap<String, Arc<RwLock<LogicType>>>, Option<Info>), String> {
Expand Down Expand Up @@ -311,7 +310,7 @@ impl LogicGroup {
if result.is_err() {
return Err(result.err().unwrap());
}
let (logic_type, mut dependencies, alias_info) = result.ok().unwrap();
let (logic_type, mut dependencies) = result.ok().unwrap();
output_dependency.append(&mut dependencies);

assert!(logic_type.len() > 0);
Expand Down Expand Up @@ -352,7 +351,7 @@ impl LogicUnion {
if result.is_err() {
return Err(result.err().unwrap());
}
let (logic_type, mut dependencies, alias_info) = result.ok().unwrap();
let (logic_type, mut dependencies) = result.ok().unwrap();
output_dependency.append(&mut dependencies);

assert!(logic_type.len() > 0);
Expand Down Expand Up @@ -405,22 +404,26 @@ impl LogicStream {
//stream type should be a reference
let stream_type = tydi_target.read().unwrap().get_stream_type();
let stream_type_value = stream_type.read().unwrap().get_value();
let stream_type = match stream_type_value.try_get_referenced_variable() {
let stream_type_var = match stream_type_value.try_get_referenced_variable() {
Some(var) => var,
None => stream_type,
};

let result = LogicType::translate_from_tydi_project(tydi_project.clone(), stream_type.clone());
let result = LogicType::translate_from_tydi_project(tydi_project.clone(), stream_type_var.clone());
if result.is_err() {
return Err(result.err().unwrap());
}
let (stream_type, mut dependencies, alias_info) = result.ok().unwrap();
let (stream_type, mut dependencies) = result.ok().unwrap();
output_dependency.append(&mut dependencies);
assert!(stream_type.len() == 1, "the type of a stream should be a single logic type, not an array");
let stream_type = stream_type[0].clone();
match stream_type {
let mut stream_type = stream_type[0].clone();
match &mut stream_type {
LogicType::Ref(r) => {
output_stream.stream_type = LogicType::Ref(r);
let all_alias = stream_type_var.read().unwrap().get_alias();
for a in all_alias {
r.add_alias(a);
}
output_stream.stream_type = LogicType::Ref(r.to_owned());
},
_ => unreachable!("should be unreachable")
}
Expand Down Expand Up @@ -452,7 +455,7 @@ impl LogicStream {
if result.is_err() {
return Err(result.err().unwrap());
}
let (user_type, mut dependencies, alias_info) = result.ok().unwrap();
let (user_type, mut dependencies) = result.ok().unwrap();
output_dependency.append(&mut dependencies);
assert!(user_type.len() == 1, "the user type of a stream should be a single logic type, not an array");
let user_type = user_type[0].clone();
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2 changes: 1 addition & 1 deletion tydi-lang-json-generator/src/json_representation_streamlet.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ impl Port {
tydi_memory_representation::PortDirection::Unknown => unreachable!(),
}
let target_port_logic_type = target_port.read().unwrap().get_logical_type();
let (result_logic_type, mut dependencies, alias_info) = LogicType::translate_from_tydi_project(tydi_project.clone(), target_port_logic_type.clone())?;
let (result_logic_type, mut dependencies) = LogicType::translate_from_tydi_project(tydi_project.clone(), target_port_logic_type.clone())?;
if result_logic_type.len() != 1 {
return Err(format!("the type of port ({}) must be a single logic type", target_port.read().unwrap().get_name()));
}
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4 changes: 2 additions & 2 deletions tydi-lang-json-generator/src/json_representation_value.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ impl Value {
TypedValue::FloatValue(v) => return Ok((Value::Float(*v), output_dependency)),
TypedValue::ClockDomainValue(v) => return Ok((Value::ClockDomain(v.clone()), output_dependency)),
TypedValue::LogicTypeValue(_) => {
let (output_value, mut dependencies, alias_info) = LogicType::translate_from_tydi_project_type_value(tydi_project, value, generate_random_str(8), None)?;
let (output_value, mut dependencies) = LogicType::translate_from_tydi_project_type_value(tydi_project, value, generate_random_str(8), None)?;
output_dependency.logic_types.append(&mut dependencies);
if output_value.len() != 1 {
return Err(format!("the output logic type should not be a logic type array"));
Expand All @@ -40,7 +40,7 @@ impl Value {
return Ok((Value::LogicType(output_value), output_dependency));
},
TypedValue::RefToVar(var) => {
let (output_value, mut dependencies, alias_info) = LogicType::translate_from_tydi_project_type_value(tydi_project, value, generate_random_str(8), Some(var.clone()))?;
let (output_value, mut dependencies) = LogicType::translate_from_tydi_project_type_value(tydi_project, value, generate_random_str(8), Some(var.clone()))?;
output_dependency.logic_types.append(&mut dependencies);
if output_value.len() != 1 {
return Err(format!("the output logic type should not be a logic type array"));
Expand Down
14 changes: 12 additions & 2 deletions tydi-lang-json-generator/src/test_project.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -696,6 +696,16 @@ fn rafflaele_generated_names_in_tydi_lang() {
type2 = type1;
type3 = type2;
type4 = type3;
entry_stream = Stats_stream;
streamlet entry_streamlet {
input_port: Stats_stream in;
}
impl entry_impl of entry_streamlet {
}
"#);
let src_pack1 = String::from(r#"
package std;
Expand Down Expand Up @@ -731,12 +741,12 @@ fn rafflaele_generated_names_in_tydi_lang() {
}
std::fs::write("./code_structure_before_evaluation.json", &project.read().unwrap().get_pretty_json()).unwrap();

project.read().unwrap().evaluate_target(format!("Stats_stream"), format!("pack")).expect("fail to evaluate");
project.read().unwrap().evaluate_target(format!("entry_impl"), format!("pack")).expect("fail to evaluate");

let code_structure = project.read().unwrap().get_pretty_json();
std::fs::write("./code_structure.json", &code_structure).unwrap();

let json_output = generate_json_representation_from_tydi_project(project.clone(), format!("Stats_stream"), format!("pack")).expect("fail to generate json");
let json_output = generate_json_representation_from_tydi_project(project.clone(), format!("entry_impl"), format!("pack")).expect("fail to generate json");
std::fs::write("./json_output.json", &json_output).unwrap();
println!("{}", json_output);
}
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