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* initial files add * joules save/reload checkpoints & many other tweaks * bump power tool versions * fixed design name * fixing sim/power clock periods * tool fixes and config improvements * removing redundant stuff * more tweaks to pass gate level sims * Update README.md * renaming tech to pdk * post syn and par power * fixed env configs * Update README.md * Update README.md * Update Makefile * minor tweaks * minor tweaks * minor changes * Update README.md * tweak * small fix * renamed test to pass example * many fixes, removing redundant keys * minor tweaks * improved report configs explanations * adding to hammer docs * Update Hammer-Overview.rst * adding power tool-supplied persistent hook * changing default toolflow from commercial to nop * fixing tool version comments * fixing typo
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../../e2e/README.md |
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include obj_dir/hammer.d | ||
vlsi_dir=$(abspath .) | ||
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# minimal flow configuration variables | ||
design ?= pass | ||
pdk ?= sky130 | ||
tools ?= nop | ||
env ?= bwrc | ||
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extra ?= # extra configs | ||
args ?= # command-line args (including step flow control) | ||
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OBJ_DIR ?= $(vlsi_dir)/build-$(pdk)-$(tools)/$(design) | ||
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# non-overlapping default configs | ||
ENV_YML ?= configs-env/$(env)-env.yml | ||
PDK_CONF ?= configs-pdk/$(pdk).yml | ||
TOOLS_CONF ?= configs-tool/$(tools).yml | ||
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# design-specific overrides of default configs | ||
DESIGN_CONF ?= configs-design/$(design)/common.yml | ||
DESIGN_PDK_CONF ?= configs-design/$(design)/$(pdk).yml | ||
SIM_CONF ?= $(if $(findstring rtl,$(MAKECMDGOALS)), configs-design/$(design)/sim-rtl.yml, \ | ||
$(if $(findstring syn,$(MAKECMDGOALS)), configs-design/$(design)/sim-syn.yml, \ | ||
$(if $(findstring par,$(MAKECMDGOALS)), configs-design/$(design)/sim-par.yml, ))) | ||
POWER_CONF ?= $(if $(findstring power-rtl,$(MAKECMDGOALS)), configs-design/$(design)/power-rtl-$(pdk).yml, \ | ||
$(if $(findstring power-syn,$(MAKECMDGOALS)), configs-design/$(design)/power-syn-$(pdk).yml, \ | ||
$(if $(findstring power-par,$(MAKECMDGOALS)), configs-design/$(design)/power-par-$(pdk).yml, ))) | ||
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PROJ_YMLS ?= $(PDK_CONF) $(TOOLS_CONF) $(DESIGN_CONF) $(DESIGN_PDK_CONF) $(SIM_CONF) $(POWER_CONF) $(extra) | ||
HAMMER_EXTRA_ARGS ?= $(foreach conf, $(PROJ_YMLS), -p $(conf)) $(args) | ||
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HAMMER_D_MK = $(OBJ_DIR)/hammer.d | ||
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build: $(HAMMER_D_MK) | ||
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$(HAMMER_D_MK): | ||
hammer-vlsi --obj_dir $(OBJ_DIR) -e $(ENV_YML) $(HAMMER_EXTRA_ARGS) build | ||
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-include $(HAMMER_D_MK) |
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# Specify clock signals | ||
vlsi.inputs.clocks: [ | ||
{name: "clk", period: "5ns", uncertainty: "0.1ns"} | ||
] | ||
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sim.inputs: | ||
defines: ["CLOCK_PERIOD=5"] | ||
defines_meta: "append" | ||
options: ["-timescale=1ns/10ps"] | ||
options_meta: append | ||
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# Placement Constraints | ||
vlsi.inputs.placement_constraints: | ||
- path: "gcd" | ||
type: toplevel | ||
x: 0 | ||
y: 0 | ||
width: 100 | ||
height: 100 | ||
margins: | ||
left: 0 | ||
right: 0 | ||
top: 0 | ||
bottom: 0 | ||
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vlsi.inputs.delays: [ | ||
{name: "reset", clock: "clk", delay: "1", direction: "input"}, | ||
{name: "operands_bits_A", clock: "clk", delay: "1", direction: "input"}, | ||
{name: "operands_bits_B", clock: "clk", delay: "1", direction: "input"}, | ||
{name: "operands_val", clock: "clk", delay: "1", direction: "input"}, | ||
{name: "operands_rdy", clock: "clk", delay: "1", direction: "output"}, | ||
{name: "result_bits_data",clock: "clk", delay: "1", direction: "output"}, | ||
{name: "result_val", clock: "clk", delay: "1", direction: "output"}, | ||
{name: "result_rdy", clock: "clk", delay: "1", direction: "input"} | ||
] |
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# Generate Make include to aid in tlow | ||
vlsi.core.build_system: make | ||
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vlsi.inputs.power_spec_type: "cpf" | ||
vlsi.inputs.power_spec_mode: "auto" | ||
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synthesis.inputs: | ||
top_module: "gcd" | ||
input_files: ["src/gcd.v"] | ||
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sim.inputs: | ||
top_module: "gcd" | ||
tb_name: "gcd_tb" | ||
tb_dut: "gcd_dut" | ||
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power.inputs: | ||
top_module: "gcd" | ||
tb_name: "gcd_tb" | ||
tb_dut: "gcd_dut" |
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# Test Joules Flow | ||
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vlsi.core.power_tool: "hammer.power.joules" | ||
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power.inputs.input_files: ["/path/to/pass.v"] | ||
power.inputs.waveforms: ["path/to/waveform"] |
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# Test Joules Flow | ||
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vlsi.core.power_tool: "hammer.power.joules" | ||
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power.inputs: | ||
level: "rtl" | ||
input_files: ["src/gcd.v"] | ||
waveforms: ["build-sky130-cm/gcd/sim-rtl-rundir/output.fsdb"] | ||
report_configs: | ||
- waveform_path: "build-sky130-cm/gcd/sim-rtl-rundir/output.fsdb" | ||
levels: 1 | ||
toggle_signal: /gcd/clk | ||
num_toggles: 1 | ||
report_name: levels-1 | ||
output_formats: | ||
- all | ||
# the following two should produce equivalent results: | ||
- waveform_path: "build-sky130-cm/gcd/sim-rtl-rundir/output.fsdb" | ||
inst: /gcd/GCDctrl0 | ||
toggle_signal: /gcd/clk | ||
num_toggles: 1 | ||
report_name: inst-GCDctrl0 | ||
output_formats: | ||
- all | ||
- waveform_path: "build-sky130-cm/gcd/sim-rtl-rundir/output.fsdb" | ||
module: gcd_control | ||
interval_size: 5ns | ||
report_name: module-gcd_control | ||
output_formats: | ||
- all | ||
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# Post-PAR Simulation | ||
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sim.inputs: | ||
level: "par" | ||
input_files: ["src/gcd_tb.v"] | ||
input_files_meta: append | ||
timing_annotated: true |
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# RTL Simulation | ||
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sim.inputs: | ||
level: "rtl" | ||
input_files: ["src/gcd.v", "src/gcd_tb.v"] | ||
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# sim.inputs.execute_sim: false |
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# Post-Synthesis Simulation | ||
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sim.inputs: | ||
level: "syn" | ||
input_files: ["src/gcd_tb.v"] | ||
input_files_meta: append | ||
timing_annotated: true | ||
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