Add generic bound

veryl-lang · Aug 28, 2024 · 5e3caab · 5e3caab
1 parent b0e9a9a
commit 5e3caab
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Showing 4 changed files with 12 additions and 3 deletions.
diff --git a/src/async_fifo/async_fifo.veryl b/src/async_fifo/async_fifo.veryl
@@ -4,7 +4,7 @@ import async_fifo_pkg::calc_default_depth;
 ///
 /// Asynchronous FIFO based on gray-code pointer.
 /// Generic parameter `S` is a module name of synchrinozer.
-pub module async_fifo::<S> #(
+pub module async_fifo::<S: synchronizer> #(
     param WIDTH             : u32  = 8                         , /// Data width
     param TYPE              : type = logic<WIDTH>              , /// Data type
     param STAGES            : u32  = 2                         , /// Stages of synchronizer

diff --git a/src/async_fifo/async_fifo_reset_sync.veryl b/src/async_fifo/async_fifo_reset_sync.veryl
@@ -1,4 +1,4 @@
-module async_fifo_reset_sync::<S> #(
+module async_fifo_reset_sync::<S: synchronizer> #(
     param MERGE_RESET      : bit = '0,
     param RESET_SYNC_STAGES: u32 = 2 ,
 ) (

diff --git a/src/async_handshake/async_handshake.veryl b/src/async_handshake/async_handshake.veryl
@@ -3,7 +3,7 @@
 ///
 /// Asynchronous data transmitter based on handshake protocol.
 /// Generic parameter `S` is a module name of synchrinoizer.
-pub module async_handshake::<S> #(
+pub module async_handshake::<S: synchronizer> #(
     param WIDTH              : u32  = 8           , /// Data width
     param TYPE               : type = logic<WIDTH>, /// Data type
     param STAGES             : u32               = 2           , /// Stages of synchrinoizer

diff --git a/src/synchronizer/synchronizer.veryl b/src/synchronizer/synchronizer.veryl
@@ -0,0 +1,9 @@
+pub proto module synchronizer #(
+    param WIDTH : u32 = 8,
+    param STAGES: u32 = 2,
+) (
+    i_clk: input  clock,
+    i_rst: input  reset,
+    i_d  : input  logic,
+    o_d  : output logic,
+);