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<a class="subtext" href="https://veryl-lang.org/blog/annoucing-veryl-0-11-0/#breaking-changes">Breaking Changes</a>
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<div class="toc-item-child">
<a class="subtext" href="https://veryl-lang.org/blog/annoucing-veryl-0-11-0/#clock-domain-annotation-support"><small>- Clock domain annotation support </small></a>
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<div class="toc-item">
<a class="subtext" href="https://veryl-lang.org/blog/annoucing-veryl-0-11-0/#new-features">New Features</a>
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<a class="subtext" href="https://veryl-lang.org/blog/annoucing-veryl-0-11-0/#support-importing-functions-into-modport"><small>- Support importing functions into modport </small></a>
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<div class="toc-item-child">
<a class="subtext" href="https://veryl-lang.org/blog/annoucing-veryl-0-11-0/#add-signed-literal-support"><small>- Add signed literal support </small></a>
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<div class="toc-item-child">
<a class="subtext" href="https://veryl-lang.org/blog/annoucing-veryl-0-11-0/#enhance-case-statement-expression"><small>- Enhance case statement&#x2F;expression </small></a>
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<a class="subtext" href="https://veryl-lang.org/blog/annoucing-veryl-0-11-0/#other-changes">Other Changes</a>
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<div class="heading-text">Announcing Veryl 0.11.0</div>
<p>The Veryl team has published a new release of Veryl, 0.11.0.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
<p>The latest version of Veryl can be downloaded from <a href="https://github.com/veryl-lang/veryl/releases/latest">release page</a>.</p>
<h1 id="breaking-changes">Breaking Changes</h1>
<h2 id="clock-domain-annotation-support">Clock domain annotation support <a style="font-size: 0.8em" href="https:&#x2F;&#x2F;github.com&#x2F;veryl-lang&#x2F;veryl/pull/789">#789</a>
</h2>
<p>If there are some clocks in a module, clock domain annotation is required.
Clock domain annotation represents which clock domain each port belongs to.
Additionally, assignment over different clock domains requires <code>unsafe (cdc)</code> block.</p>
<pre data-lang="veryl" style="background-color:#393939;color:#dedede;" class="language-veryl "><code class="language-veryl" data-lang="veryl"><span style="color:#fed6af;">module </span><span>ModuleA (
</span><span> </span><span style="color:#a0cfa1;">//</span><span style="color:#87ae86;"> clock domain &#39;a
</span><span> i_clk_a: </span><span style="color:#fffb9d;">input</span><span> &#39;a </span><span style="color:#fffb9d;">clock</span><span>,
</span><span> i_dat_a: </span><span style="color:#fffb9d;">input</span><span> &#39;a </span><span style="color:#fffb9d;">logic</span><span>,
</span><span> o_dat_a: </span><span style="color:#fffb9d;">output</span><span> &#39;a </span><span style="color:#fffb9d;">logic</span><span>,
</span><span>
</span><span> </span><span style="color:#a0cfa1;">//</span><span style="color:#87ae86;"> clock domain &#39;b
</span><span> i_clk_b: </span><span style="color:#fffb9d;">input</span><span> &#39;b </span><span style="color:#fffb9d;">clock</span><span>,
</span><span> i_dat_b: </span><span style="color:#fffb9d;">input</span><span> &#39;b </span><span style="color:#fffb9d;">logic</span><span>,
</span><span> o_dat_b: </span><span style="color:#fffb9d;">output</span><span> &#39;b </span><span style="color:#fffb9d;">logic</span><span>,
</span><span>) {
</span><span> </span><span style="color:#fed6af;">unsafe</span><span> (cdc) {
</span><span> </span><span style="color:#a0cfa1;">//</span><span style="color:#87ae86;"> assignment from &#39;a domain to &#39;b domain
</span><span> </span><span style="color:#fed6af;">assign </span><span>o_dat_b = i_dat_a;
</span><span> }
</span><span>}
</span></code></pre>
<h1 id="new-features">New Features</h1>
<h2 id="support-importing-functions-into-modport">Support importing functions into modport <a style="font-size: 0.8em" href="https:&#x2F;&#x2F;github.com&#x2F;veryl-lang&#x2F;veryl/pull/742">#742</a>
</h2>
<p>Function in interface can be imported through <code>import</code> direction in <code>modport</code> declaration.</p>
<pre data-lang="veryl" style="background-color:#393939;color:#dedede;" class="language-veryl "><code class="language-veryl" data-lang="veryl"><span style="color:#fed6af;">interface </span><span>InterfaceA {
</span><span> </span><span style="color:#fed6af;">var </span><span>a: </span><span style="color:#fffb9d;">logic</span><span>;
</span><span>
</span><span> </span><span style="color:#fed6af;">function </span><span>get_a () -&gt; </span><span style="color:#fffb9d;">logic</span><span> {
</span><span> </span><span style="color:#fed6af;">return </span><span>a;
</span><span> }
</span><span>
</span><span> </span><span style="color:#fed6af;">modport </span><span>slave {
</span><span> a : </span><span style="color:#fffb9d;">input</span><span> ,
</span><span> get_a: </span><span style="color:#fed6af;">import</span><span>,
</span><span> }
</span><span>}
</span></code></pre>
<h2 id="add-signed-literal-support">Add signed literal support <a style="font-size: 0.8em" href="https:&#x2F;&#x2F;github.com&#x2F;veryl-lang&#x2F;veryl/pull/770">#770</a>
</h2>
<p>Signed literal with <code>s</code> prefix is supported.</p>
<pre data-lang="veryl" style="background-color:#393939;color:#dedede;" class="language-veryl "><code class="language-veryl" data-lang="veryl"><span style="color:#fed6af;">module </span><span>ModuleA {
</span><span> </span><span style="color:#fed6af;">local </span><span>a: </span><span style="color:#fffb9d;">u32</span><span> = 32&#39;sb1111;
</span><span> </span><span style="color:#fed6af;">local </span><span>b: </span><span style="color:#fffb9d;">u32</span><span> = 32&#39;so7777;
</span><span> </span><span style="color:#fed6af;">local </span><span>c: </span><span style="color:#fffb9d;">u32</span><span> = 32&#39;sd9999;
</span><span> </span><span style="color:#fed6af;">local </span><span>d: </span><span style="color:#fffb9d;">u32</span><span> = 32&#39;shffff;
</span><span>}
</span></code></pre>
<h2 id="enhance-case-statement-expression">Enhance case statement/expression <a style="font-size: 0.8em" href="https:&#x2F;&#x2F;github.com&#x2F;veryl-lang&#x2F;veryl/pull/783">#783</a>
</h2>
<p>As case item, range expression and expression with constant value can be used.
<code>switch</code> which has arbitrary expression as the condition items is added too.</p>
<pre data-lang="veryl" style="background-color:#393939;color:#dedede;" class="language-veryl "><code class="language-veryl" data-lang="veryl"><span style="color:#fed6af;">module </span><span>Module16 {
</span><span> </span><span style="color:#fed6af;">local </span><span>P: </span><span style="color:#fffb9d;">bit</span><span> = 1;
</span><span>
</span><span> </span><span style="color:#fed6af;">var </span><span>a: </span><span style="color:#fffb9d;">logic</span><span>;
</span><span> </span><span style="color:#fed6af;">var </span><span>b: </span><span style="color:#fffb9d;">logic</span><span>;
</span><span> </span><span style="color:#fed6af;">let </span><span>x: </span><span style="color:#fffb9d;">logic</span><span> = 1;
</span><span> </span><span style="color:#fed6af;">let </span><span>y: </span><span style="color:#fffb9d;">logic</span><span> = 1;
</span><span>
</span><span> </span><span style="color:#fed6af;">always_comb</span><span> {
</span><span> </span><span style="color:#fed6af;">case </span><span>x {
</span><span> 5..=7 : a = 1;
</span><span> P - 1 : a = 1;
</span><span> </span><span style="color:#a0cfa1;">//</span><span style="color:#87ae86;"> Error because y is not constant value
</span><span> </span><span style="color:#a0cfa1;">//</span><span style="color:#87ae86;">y - 1 : a = 1;
</span><span> </span><span style="color:#fed6af;">default</span><span>: a = 1;
</span><span> }
</span><span> }
</span><span>
</span><span> </span><span style="color:#fed6af;">always_comb</span><span> {
</span><span> </span><span style="color:#fed6af;">switch</span><span> {
</span><span> </span><span style="color:#a0cfa1;">//</span><span style="color:#87ae86;"> arbitrary expression includuing variable can be used
</span><span> y == 0 : b = 1;
</span><span> </span><span style="color:#fed6af;">default</span><span>: b = 1;
</span><span> }
</span><span> }
</span><span>}
</span></code></pre>
<h1 id="other-changes">Other Changes</h1>
<p>Check out everything that changed in <a href="https://github.com/veryl-lang/veryl/releases/tag/v0.11.0">Release v0.11.0</a>.</p>


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