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Vector Support for User BEL in Verilog. (#222)
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* Vector support for file parser

* Fixes to parsing and verilog

* Backwards compat for indivudal port decleration
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@A-Kibats
A-Kibats authored Aug 8, 2024
1 parent 3579a3d commit 73f57a0
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5 changes: 5 additions & 0 deletions FABulous/fabric_definition/Bel.py
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,8 @@ class Bel:
The feature map of the BEL.
withUserCLK : bool
Whether the BEL has userCLK port. Default is False.
individually_declared : bool
Indicates if ports are individually declared. Default is False.
"""

src: str
Expand All @@ -53,6 +55,7 @@ class Bel:
configBit: int
belFeatureMap: dict[str, dict] = field(default_factory=dict)
withUserCLK: bool = False
individually_declared: bool = False

def __init__(
self,
Expand All @@ -65,6 +68,7 @@ def __init__(
configBit: int,
belMap: dict[str, dict],
userCLK: bool,
individually_declared: bool,
) -> None:
self.src = src
self.prefix = prefix
Expand All @@ -78,3 +82,4 @@ def __init__(
self.configBit = configBit
self.belFeatureMap = belMap
self.withUserCLK = userCLK
self.individually_declared = individually_declared
102 changes: 11 additions & 91 deletions FABulous/fabric_files/FABulous_project_template_verilog/Tile/DSP/DSP_bot/MULADD.v
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Original file line number Diff line number Diff line change
Expand Up @@ -20,74 +20,17 @@ ACC=3,
signExtension=4,
ACCout=5
*)
module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, Q19, Q18, Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, clr, UserCLK, ConfigBits);
parameter NoConfigBits = 6;// has to be adjusted manually (we don't use an arithmetic parser for the value)
// IMPORTANT: this has to be in a dedicated line
input A7;// operand A
input A6;
input A5;
input A4;
input A3;
input A2;
input A1;
input A0;
input B7;// operand B
input B6;
input B5;
input B4;
input B3;
input B2;
input B1;
input B0;
input C19;// operand C
input C18;
input C17;
input C16;
input C15;
input C14;
input C13;
input C12;
input C11;
input C10;
input C9;
input C8;
input C7;
input C6;
input C5;
input C4;
input C3;
input C2;
input C1;
input C0;
output Q19;// result
output Q18;
output Q17;
output Q16;
output Q15;
output Q14;
output Q13;
output Q12;
output Q11;
output Q10;
output Q9;
output Q8;
output Q7;
output Q6;
output Q5;
output Q4;
output Q3;
output Q2;
output Q1;
output Q0;

input clr;
(* FABulous, EXTERNAL, SHARED_PORT *) input UserCLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
module MULADD #(parameter NoConfigBits = 6)(
// ConfigBits has to be adjusted manually (we don't use an arithmetic parser for the value)
input [7:0] A, // operand A
input [7:0] B, // operand B
input [19:0] C, // operand C
output [19:0] Q,// result
input clr,
(* FABulous, EXTERNAL, SHARED_PORT *) input UserCLK, // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
(* FABulous, GLOBAL *) input [NoConfigBits-1:0] ConfigBits;

wire [7:0] A; // port A read data
wire [7:0] B; // port B read data
wire [19:0] C; // port B read data
(* FABulous, GLOBAL *) input [NoConfigBits-1:0] ConfigBits
);
reg [7:0] A_reg; // port A read data register
reg [7:0] B_reg; // port B read data register
reg [19:0] C_reg; // port B read data register
Expand All @@ -100,10 +43,6 @@ module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C
wire [15:0] product;
wire [19:0] product_extended;

assign A = {A7,A6,A5,A4,A3,A2,A1,A0};
assign B = {B7,B6,B5,B4,B3,B2,B1,B0};
assign C = {C19,C18,C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0};

assign OPA = ConfigBits[0] ? A_reg : A;
assign OPB = ConfigBits[1] ? B_reg : B;
assign OPC = ConfigBits[2] ? C_reg : C;
Expand All @@ -117,26 +56,7 @@ module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C

assign sum = product_extended + sum_in;

assign Q19 = ConfigBits[5] ? ACC[19] : sum[19];
assign Q18 = ConfigBits[5] ? ACC[18] : sum[18];
assign Q17 = ConfigBits[5] ? ACC[17] : sum[17];
assign Q16 = ConfigBits[5] ? ACC[16] : sum[16];
assign Q15 = ConfigBits[5] ? ACC[15] : sum[15];
assign Q14 = ConfigBits[5] ? ACC[14] : sum[14];
assign Q13 = ConfigBits[5] ? ACC[13] : sum[13];
assign Q12 = ConfigBits[5] ? ACC[12] : sum[12];
assign Q11 = ConfigBits[5] ? ACC[11] : sum[11];
assign Q10 = ConfigBits[5] ? ACC[10] : sum[10];
assign Q9 = ConfigBits[5] ? ACC[9] : sum[9];
assign Q8 = ConfigBits[5] ? ACC[8] : sum[8];
assign Q7 = ConfigBits[5] ? ACC[7] : sum[7];
assign Q6 = ConfigBits[5] ? ACC[6] : sum[6];
assign Q5 = ConfigBits[5] ? ACC[5] : sum[5];
assign Q4 = ConfigBits[5] ? ACC[4] : sum[4];
assign Q3 = ConfigBits[5] ? ACC[3] : sum[3];
assign Q2 = ConfigBits[5] ? ACC[2] : sum[2];
assign Q1 = ConfigBits[5] ? ACC[1] : sum[1];
assign Q0 = ConfigBits[5] ? ACC[0] : sum[0];
assign Q = ConfigBits[5] ? ACC : sum;

always @ (posedge UserCLK)
begin
Expand Down
33 changes: 14 additions & 19 deletions ...us/fabric_files/FABulous_project_template_verilog/Tile/LUT4AB/LUT4c_frame_config_dffesr.v
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Original file line number Diff line number Diff line change
Expand Up @@ -33,22 +33,17 @@ FF=16,
IOmux=17,
SET_NORESET=18
*)
module LUT4c_frame_config_dffesr (I0, I1, I2, I3, O, Ci, Co, SR, EN, UserCLK, ConfigBits);
parameter NoConfigBits = 19 ; // has to be adjusted manually (we don't use an arithmetic parser for the value)
// IMPORTANT: this has to be in a dedicated line
input I0; // LUT inputs
input I1;
input I2;
input I3;
output O; // LUT output (combinatorial or FF)
input Ci; // carry chain input
output Co; // carry chain output
input SR; // SHARED_RESET
input EN; // SHARED_ENABLE
(* FABulous, EXTERNAL, SHARED_PORT *) input UserCLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
(* FABulous, GLOBAL *) input [NoConfigBits-1 : 0] ConfigBits;

module LUT4c_frame_config_dffesr #(parameter NoConfigBits = 19)(
// ConfigBits has to be adjusted manually (we don't use an arithmetic parser for the value)
input [3:0] I, // Vector for I0, I1, I2, I3
output O, // Single output for LUT result
input Ci, // Carry chain input
output Co, // Carry chain output
input SR, // SHARED_RESET
input EN, // SHARED_ENABLE
(* FABulous, EXTERNAL, SHARED_PORT *) input UserCLK, // External and shared clock
(* FABulous, GLOBAL *) input [NoConfigBits-1:0] ConfigBits // Config bits as vector
);
localparam LUT_SIZE = 4;
localparam N_LUT_flops = 2 ** LUT_SIZE;

Expand All @@ -68,13 +63,13 @@ module LUT4c_frame_config_dffesr (I0, I1, I2, I3, O, Ci, Co, SR, EN, UserCLK, Co

//assign I0mux = c_I0mux ? Ci : I0;
my_mux2 my_mux2_I0mux(
.A0(I0),
.A0(I[0]),
.A1(Ci),
.S(c_I0mux),
.X(I0mux)
);

assign LUT_index = {I3,I2,I1,I0mux};
assign LUT_index = {I[3],I[2],I[1],I0mux};

// The LUT is just a multiplexer
// for a first shot, I am using a 16:1
Expand Down Expand Up @@ -138,7 +133,7 @@ module LUT4c_frame_config_dffesr (I0, I1, I2, I3, O, Ci, Co, SR, EN, UserCLK, Co
.X(O)
);

assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2);// iCE40 like carry chain (as this is supported in Yosys; would normally go for fractured LUT
assign Co = (Ci & I[1]) | (Ci & I[2]) | (I[1] & I[2]);// iCE40 like carry chain (as this is supported in Yosys; would normally go for fractured LUT)

always @ (posedge UserCLK) begin
if (EN) begin
Expand Down
67 changes: 32 additions & 35 deletions ...ous/fabric_files/FABulous_project_template_verilog/Tile/LUT4AB/MUX8LUT_frame_config_mux.v
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Original file line number Diff line number Diff line change
Expand Up @@ -17,27 +17,24 @@
c0=0,
c1=1
*)
module MUX8LUT_frame_config_mux (A, B, C, D, E, F, G, H, S0, S1, S2, S3, M_AB, M_AD, M_AH, M_EF, ConfigBits);
parameter NoConfigBits = 2;// has to be adjusted manually (we don't use an arithmetic parser for the value)
// IMPORTANT: this has to be in a dedicated line
input A; // MUX inputs
input B;
input C;
input D;
input E;
input F;
input G;
input H;
input S0;
input S1;
input S2;
input S3;
output M_AB;
output M_AD;
output M_AH;
output M_EF;
module MUX8LUT_frame_config_mux #(parameter NoConfigBits = 2)(
// ConfigBits has to be adjusted manually (we don't use an arithmetic parser for the value)
input A, // MUX inputs
input B,
input C,
input D,
input E,
input F,
input G,
input H,
input [3:0] S,
output M_AB,
output M_AD,
output M_AH,
output M_EF,
// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
(* FABulous, GLOBAL *) input [NoConfigBits-1:0] ConfigBits;
(* FABulous, GLOBAL *) input [NoConfigBits-1:0] ConfigBits
);

wire AB, CD, EF, GH;
wire sCD, sEF, sGH, sEH;
Expand All @@ -50,11 +47,11 @@ module MUX8LUT_frame_config_mux (A, B, C, D, E, F, G, H, S0, S1, S2, S3, M_AB, M
assign c1 = ConfigBits[1];

// see figure (column-wise left-to-right)
//assign AB = S0 ? B : A;
//assign AB = S[0] ? B : A;
my_mux2 my_mux2_AB(
.A0(A),
.A1(B),
.S(S0),
.S(S[0]),
.X(AB)
);
//assign CD = sCD ? D : C;
Expand All @@ -79,17 +76,17 @@ module MUX8LUT_frame_config_mux (A, B, C, D, E, F, G, H, S0, S1, S2, S3, M_AB, M
.X(GH)
);

//assign sCD = c0 ? S0 : S1;
//assign sCD = c0 ? S[0] : S[1];
my_mux2 my_mux2_sCD(
.A0(S1),
.A1(S0),
.A0(S[1]),
.A1(S[0]),
.S(c0),
.X(sCD)
);
//assign sEF = c1 ? S0 : S2;
//assign sEF = c1 ? S[0] : S[2];
my_mux2 my_mux2_sEF(
.A0(S2),
.A1(S0),
.A0(S[2]),
.A1(S[0]),
.S(c1),
.X(sEF)
);
Expand All @@ -100,19 +97,19 @@ module MUX8LUT_frame_config_mux (A, B, C, D, E, F, G, H, S0, S1, S2, S3, M_AB, M
.S(c0),
.X(sGH)
);
//assign sEH = c1 ? S1 : S3;
//assign sEH = c1 ? S[1] : S[3];
my_mux2 my_mux2_sEH(
.A0(S3),
.A1(S1),
.A0(S[3]),
.A1(S[1]),
.S(c1),
.X(sEH)
);

//assign AD = S1 ? CD : AB;
//assign AD = S[1] ? CD : AB;
my_mux2 my_mux2_AD(
.A0(AB),
.A1(CD),
.S(S1),
.S(S[1]),
.X(AD)
);
//assign EH = sEH ? GH : EF;
Expand All @@ -123,11 +120,11 @@ module MUX8LUT_frame_config_mux (A, B, C, D, E, F, G, H, S0, S1, S2, S3, M_AB, M
.X(EH)
);

//assign AH = S3 ? EH : AD;
//assign AH = S[3] ? EH : AD;
my_mux2 my_mux2_AH(
.A0(AD),
.A1(EH),
.S(S3),
.S(S[3]),
.X(AH)
);

Expand Down
18 changes: 6 additions & 12 deletions FABulous/fabric_files/FABulous_project_template_verilog/Tile/RAM_IO/Config_access.v
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Original file line number Diff line number Diff line change
Expand Up @@ -4,20 +4,14 @@ C_bit1=1,
C_bit2=2,
C_bit3=3
*)
module Config_access (C_bit0, C_bit1, C_bit2, C_bit3, ConfigBits);
parameter NoConfigBits = 4;// has to be adjusted manually (we don't use an arithmetic parser for the value)
module Config_access #(parameter NoConfigBits = 4)(
// ConfigBits has to be adjusted manually (we don't use an arithmetic parser for the value)
// Pin0
(* FABulous, EXTERNAL *)output C_bit0; // EXTERNAL
(* FABulous, EXTERNAL *)output C_bit1; // EXTERNAL
(* FABulous, EXTERNAL *)output C_bit2; // EXTERNAL
(* FABulous, EXTERNAL *)output C_bit3; // EXTERNAL
(* FABulous, EXTERNAL *)output [3:0] C_bit, // EXTERNAL
// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
(* FABulous, GLOBAL *)input [NoConfigBits-1:0] ConfigBits;

(* FABulous, GLOBAL *)input [NoConfigBits-1:0] ConfigBits
);
// we just wire configuration bits to fabric top
assign C_bit0 = ConfigBits[0];
assign C_bit1 = ConfigBits[1];
assign C_bit2 = ConfigBits[2];
assign C_bit3 = ConfigBits[3];
assign C_bit = ConfigBits;

endmodule
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