Build FABulous package with setuptools

Update pyproject.toml to build FABulous package with setuptools. Use setuptools-scm for autoamtic project version generation. Add FABulous as package script to make it callable directlty from shell. Add bit_gen as package script and add main function to it. Update import statements in all python modules to absolue imports of FABulous modules and and remove unused imports. Update "fabric_gen" github workflow: - Use new FABulous structure - Update external actions Update gitignore. Some cosmetic fixes. Signed-off-by: Jonas K. <[email protected]>
FPGA-Research · Sep 8, 2023 · 794068a · 794068a
1 parent 140b17a
commit 794068a
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diff --git a/.github/workflows/fabric_gen.yml b/.github/workflows/fabric_gen.yml
@@ -11,15 +11,15 @@ jobs:
         runs-on: ubuntu-latest
 
         steps:
-            - uses: actions/checkout@v2
+            - uses: actions/checkout@v4
               with:
                   submodules: recursive
             - name: Set up Python 3.9
-              uses: actions/setup-python@v2
+              uses: actions/setup-python@v4
               with:
                   python-version: 3.9
             - name: Set up OSS CAD suite
-              uses: YosysHQ/setup-oss-cad-suite@v1
+              uses: YosysHQ/setup-oss-cad-suite@v2
             - name: Install dependencies
               run: |
                   python3 -m pip install --upgrade pip
@@ -31,15 +31,16 @@ jobs:
             - name: Lint with flake8
               run: |
                   # stop the build if there are Python syntax errors or undefined names
-                  flake8 FABulous/fabric_generator/ --count --select=E9,F63,F7,F82 --show-source --statistics
+                  flake8 FABulous/**/*.py --count --select=E9,F63,F7,F82 --show-source --statistics
                   # exit-zero treats all errors as warnings. The GitHub editor is 127 chars wide
-                  flake8 FABulous/fabric_generator --count --exit-zero --max-complexity=10 --max-line-length=127 --statistics
+                  flake8 FABulous/**/*.py --count --exit-zero --max-complexity=10 --max-line-length=127 --statistics
+            - name: Install FABulous
+              run: |
+                  pip3 install -e .
             - name: Run fabric generator flow
               run: |
-                  export FAB_ROOT=.
-                  python3.9 FABulous/FABulous.py -c demo
-                  python3.9 FABulous/FABulous.py demo --script ./demo/FABulous.tcl
-
+                  FABulous -c demo
+                  FABulous demo --script ./demo/FABulous.tcl
             - name: Run simulation smoketest
               run: |
                   cd ./demo/Test

diff --git a/.gitignore b/.gitignore
@@ -1 +1,3 @@
 demo/
+*.egg-info/
+__pycache__/
diff --git a/FABulous/FABulous.py b/FABulous/FABulous.py
@@ -33,15 +33,16 @@
 from typing import List, Literal
 
 import docker
-import fabric_generator.code_generator as codeGen
-import fabric_generator.file_parser as fileParser
-import fabric_generator.model_generation_npnr as model_gen_npnr
-import fabric_generator.model_generation_vpr as model_gen_vpr
-from fabric_generator.code_generation_Verilog import VerilogWriter
-from fabric_generator.code_generation_VHDL import VHDLWriter
-from fabric_generator.fabric import Fabric
-from fabric_generator.fabric_gen import FabricGenerator
-from fabric_generator.utilities import GetFabric, genFabricObject
+
+from FABulous.fabric_generator import code_generator as codeGen
+from FABulous.fabric_generator import file_parser as fileParser
+from FABulous.fabric_generator import model_generation_npnr as model_gen_npnr
+from FABulous.fabric_generator import model_generation_vpr as model_gen_vpr
+from FABulous.fabric_generator.code_generation_Verilog import VerilogWriter
+from FABulous.fabric_generator.code_generation_VHDL import VHDLWriter
+from FABulous.fabric_generator.fabric import Fabric
+from FABulous.fabric_generator.fabric_gen import FabricGenerator
+from FABulous.fabric_generator.utilities import GetFabric, genFabricObject
 
 readline.set_completer_delims(' \t\n')
 

diff --git a/FABulous/fabric_cad/__init__.py b/FABulous/fabric_cad/__init__.py
diff --git a/FABulous/fabric_cad/bit_gen.py b/FABulous/fabric_cad/bit_gen.py
@@ -1,21 +1,17 @@
-# Python 3
-from array import array
+#!/usr/bin/env python
+
+import pickle
 import re
 import sys
-from contextlib import redirect_stdout
-from io import StringIO
-import math
-import os
-import numpy
-import pickle
-import csv
-from fasm import * #Remove this line if you do not have the fasm library installed and will not be generating a bitstream
-
+
+from fasm import *  # Remove this line if you do not have the fasm library installed and will not be generating a bitstream
+
+
 def replace(string, substitutions):
     substrings = sorted(substitutions, key=len, reverse=True)
     regex = re.compile('|'.join(map(re.escape, substrings)))
     return regex.sub(lambda match: substitutions[match.group(0)], string)
-    
+
 def bitstring_to_bytes(s):
     return int(s, 2).to_bytes((len(s) + 7) // 8, byteorder='big')
 
@@ -52,7 +48,7 @@ def genBitstream(fasmFile: str, specFile: str, bitstreamFile: str):
             featureName = ".".join((tileVals[1], tileVals[2]))
             if tileLoc not in specDict["TileMap"].keys():
                 raise Exception("Tile found in fasm file not found in bitstream spec")
-            tileType = specDict["TileMap"][tileLoc] #Set the necessary bits high 
+            tileType = specDict["TileMap"][tileLoc] #Set the necessary bits high
             if featureName in specDict["TileSpecs"][tileLoc].keys():
                 if specDict["TileSpecs"][tileLoc][featureName]:
                     for bitIndex in specDict["TileSpecs"][tileLoc][featureName]:
@@ -106,7 +102,6 @@ def genBitstream(fasmFile: str, specFile: str, bitstreamFile: str):
             tileKey = f"X{x}Y{y}"
             curStr = ",".join((tileKey, specDict["TileMap"][tileKey], str(x), str(y)))
             curStr += "\n"
-            bitPos = 0
 
             for frameIndex in range(MaxFramesPerCol):
                 #print (tileDict[tileKey]) #:FrameBitsPerRow*frameIndex
@@ -137,9 +132,9 @@ def genBitstream(fasmFile: str, specFile: str, bitstreamFile: str):
             bitStr += bitstring_to_bytes(frame_select_temp)
             bitStr += bit_array[i][j]
 
-                        
+
     #Note - format in output file is line by line:
-    #Tile Loc, Tile Type, X, Y, bits...... \n 
+    #Tile Loc, Tile Type, X, Y, bits...... \n
     #Each line is one tile
     print(outStr, file = open(bitstreamFile.replace("bin","fasm"), "w+"))
     print(verilog_str, file = open(bitstreamFile.replace("bin","vh"), "w+"))
@@ -152,7 +147,7 @@ def genBitstream(fasmFile: str, specFile: str, bitstreamFile: str):
 class Tile:
     tileType = ""
     bels = []
-    wires = [] 
+    wires = []
     atomicWires = [] #For storing single wires (to handle cascading and termination)
     pips = []
     belPorts = set()
@@ -162,7 +157,7 @@ class Tile:
 
     x = -1 #Init with negative values to ease debugging
     y = -1
-    
+
     def __init__(self, inType):
         self.tileType = inType
 
@@ -214,39 +209,41 @@ def getTileAndWireByWireDest(self, loc: str, dest: str, jumps: bool = True):
                             return (tile, wire, i)
 
         return None
-    
+
 #####################################################################################
 # Main
 #####################################################################################
 
-#Strip arguments
-caseProcessedArguments = list(map(lambda x: x.strip(), sys.argv))
-processedArguments = list(map(lambda x: x.lower(), caseProcessedArguments))
-flagRE = re.compile("-\S*")
+def bit_gen():
+    #Strip arguments
+    caseProcessedArguments = list(map(lambda x: x.strip(), sys.argv))
+    processedArguments = list(map(lambda x: x.lower(), caseProcessedArguments))
+    flagRE = re.compile("-\S*")
+
+    if ('-genBitstream'.lower() in str(sys.argv).lower()):
+        argIndex = processedArguments.index('-genBitstream'.lower())
 
-if ('-genBitstream'.lower() in str(sys.argv).lower()):
-    argIndex = processedArguments.index('-genBitstream'.lower())
-
-    if len(processedArguments) <= argIndex + 3:
-        raise ValueError('\nError: -genBitstream expect three file names - the fasm file, the spec file and the output file')
-    elif (flagRE.match(caseProcessedArguments[argIndex + 1])
-        or flagRE.match(caseProcessedArguments[argIndex + 2]) 
-        or flagRE.match(caseProcessedArguments[argIndex + 3])):
-        raise ValueError('\nError: -genBitstream expect three file names, but found a flag in the arguments:'
-            f' {caseProcessedArguments[argIndex + 1]}, {caseProcessedArguments[argIndex + 2]}, {caseProcessedArguments[argIndex + 3]}\n')
+        if len(processedArguments) <= argIndex + 3:
+            raise ValueError('\nError: -genBitstream expect three file names - the fasm file, the spec file and the output file')
+        elif (flagRE.match(caseProcessedArguments[argIndex + 1])
+            or flagRE.match(caseProcessedArguments[argIndex + 2])
+            or flagRE.match(caseProcessedArguments[argIndex + 3])):
+            raise ValueError('\nError: -genBitstream expect three file names, but found a flag in the arguments:'
+                f' {caseProcessedArguments[argIndex + 1]}, {caseProcessedArguments[argIndex + 2]}, {caseProcessedArguments[argIndex + 3]}\n')
 
-    FasmFileName  = caseProcessedArguments[argIndex + 1]
-    SpecFileName  = caseProcessedArguments[argIndex + 2]
-    OutFileName  = caseProcessedArguments[argIndex + 3]
+        FasmFileName  = caseProcessedArguments[argIndex + 1]
+        SpecFileName  = caseProcessedArguments[argIndex + 2]
+        OutFileName  = caseProcessedArguments[argIndex + 3]
 
-    genBitstream(FasmFileName, SpecFileName, OutFileName)
+        genBitstream(FasmFileName, SpecFileName, OutFileName)
 
 
 
-if ('-help'.lower() in str(sys.argv).lower()) or ('-h' in str(sys.argv).lower()):
-    print('')   
-    print('Options/Switches')   
-    print('  -genBitstream foo.fasm spec.txt bitstream.txt - generates a bitstream - the first file is the fasm file, the second is the bitstream spec and the third is the fasm file to write to')
-
+    if ('-help'.lower() in str(sys.argv).lower()) or ('-h' in str(sys.argv).lower()):
+        print('')
+        print('Options/Switches')
+        print('  -genBitstream foo.fasm spec.txt bitstream.txt - generates a bitstream - the first file is the fasm file, the second is the bitstream spec and the third is the fasm file to write to')
 
 
+if __name__ == "__main__":
+    bit_gen()
diff --git a/FABulous/fabric_generator/code_generation_VHDL.py b/FABulous/fabric_generator/code_generation_VHDL.py
@@ -1,11 +1,8 @@
-from typing import Literal, Tuple
-import os
 import math
 import re
 
-from fabric_generator.fabric import Fabric, Tile, Port, Bel, IO
-from fabric_generator.code_generator import codeGenerator
-from fabric_generator.fabric import ConfigBitMode
+from FABulous.fabric_generator.code_generator import codeGenerator
+from FABulous.fabric_generator.fabric import IO
 
 
 class VHDLWriter(codeGenerator):

diff --git a/FABulous/fabric_generator/code_generation_Verilog.py b/FABulous/fabric_generator/code_generation_Verilog.py
@@ -1,9 +1,8 @@
-from typing import Literal
 import math
 import re
 
-from fabric_generator.fabric import Tile, Bel, ConfigBitMode, IO
-from fabric_generator.code_generator import codeGenerator
+from FABulous.fabric_generator.code_generator import codeGenerator
+from FABulous.fabric_generator.fabric import IO
 
 
 class VerilogWriter(codeGenerator):

diff --git a/FABulous/fabric_generator/code_generator.py b/FABulous/fabric_generator/code_generator.py
@@ -1,6 +1,7 @@
 import abc
 from typing import List, Tuple
-from fabric_generator.fabric import Bel, IO, ConfigBitMode
+
+from FABulous.fabric_generator.fabric import IO
 
 
 class codeGenerator(abc.ABC):
@@ -87,7 +88,7 @@ def addHeaderEnd(self, name: str, indentLevel=0):
         Add end to header. Only useful with VHDL.
 
         Examples :
-            | Verilog: 
+            | Verilog:
             | VHDL: end entity **name**;
 
         Args:
@@ -136,7 +137,7 @@ def addParameter(self, name: str, type, value, indentLevel=0):
         Args:
             name (str): name of the parameter
             type (_type_): type of the parameter. Only useful with VHDL.
-            value (_type_): value of the parameter. 
+            value (_type_): value of the parameter.
             indentLevel (int, optional): The indentation Level. Defaults to 0.
         """
         pass
@@ -221,7 +222,7 @@ def addDesignDescriptionStart(self, name: str, indentLevel=0):
     @abc.abstractmethod
     def addDesignDescriptionEnd(self, indentLevel=0):
         """
-        Add end of design description. 
+        Add end of design description.
 
         Examples :
             | Verilog: endmodule
@@ -274,7 +275,7 @@ def addConnectionVector(self, name: str, startIndex, endIndex=0, indentLevel=0):
 
         Args:
             name (str): name of the connection
-            startIndex : Start index of the vector. Can be a string. 
+            startIndex : Start index of the vector. Can be a string.
             endIndex (int, optional): End index of the vector. Can be a string. Defaults to 0.
             indentLevel (int, optional): The indentation Level. Defaults to 0.
         """
@@ -286,7 +287,7 @@ def addLogicStart(self, indentLevel=0):
         Add start of logic. Only useful with VHDL.
 
         Examples :
-            | Verilog: 
+            | Verilog:
             | VHDL: begin
 
         Args:
@@ -319,7 +320,7 @@ def addInstantiation(self, compName: str, compInsName: str, portsPairs: List[Tup
             |             . **paramPorts[1]** (**paramSignals[1]**),
             |             ...
             |             . **paramPorts[n]** (**paramSignals[n]**)
-            |             ) ( 
+            |             ) (
             |             . **compPorts[0]** (**signals[0]**),
             |             . **compPorts[1]** (**signals[1]**),
             |             ...
@@ -391,9 +392,9 @@ def addFlipFlopChain(self, configBits: int, indentLevel=0):
     @abc.abstractmethod
     def addAssignScalar(self, left, right, delay=0, indentLevel=0):
         """
-        Add a scalar assign statement. Delay is provided by currently not being used by any of the code generator. 
-        If **right** is a list, it will be concatenated. 
-        Verilog will be concatenated with comma ','. 
+        Add a scalar assign statement. Delay is provided by currently not being used by any of the code generator.
+        If **right** is a list, it will be concatenated.
+        Verilog will be concatenated with comma ','.
         VHDL will be concatenated with ampersand '&'.
 
         Examples :

diff --git a/FABulous/fabric_generator/fabric_gen.py b/FABulous/fabric_generator/fabric_gen.py
@@ -16,24 +16,24 @@
 # SPDX-License-Identifier: Apache-2.0
 
 
-import re
+import csv
+import logging
 import math
 import os
+import re
 import string
-import csv
 from typing import Dict, List, Tuple
-import logging
-
 
 from fasm import *  # Remove this line if you do not have the fasm library installed and will not be generating a bitstream
 
-
-from fabric_generator.file_parser import parseMatrix, parseConfigMem, parseList
-from fabric_generator.fabric import IO, Direction, MultiplexerStyle, ConfigBitMode
-from fabric_generator.fabric import Fabric, Tile, Port, SuperTile, ConfigMem
-from fabric_generator.code_generation_VHDL import VHDLWriter
-from fabric_generator.code_generation_Verilog import VerilogWriter
-from fabric_generator.code_generator import codeGenerator
+from FABulous.fabric_generator.code_generation_Verilog import VerilogWriter
+from FABulous.fabric_generator.code_generation_VHDL import VHDLWriter
+from FABulous.fabric_generator.code_generator import codeGenerator
+from FABulous.fabric_generator.fabric import (IO, ConfigBitMode, ConfigMem, Direction,
+                                      Fabric, MultiplexerStyle, Port,
+                                      SuperTile, Tile)
+from FABulous.fabric_generator.file_parser import (parseConfigMem, parseList,
+                                           parseMatrix)
 
 SWITCH_MATRIX_DEBUG_SIGNAL = True
 logger = logging.getLogger(__name__)
@@ -1763,7 +1763,7 @@ def split_port(p):
 
         self.writer.addComment(
             "External IO port", onNewLine=True, indentLevel=2)
-        for name, group in sorted(portGroups.items(), key=lambda x:x[0]): 
+        for name, group in sorted(portGroups.items(), key=lambda x:x[0]):
             if self.fabric.numberOfBRAMs > 0 and ("RAM2FAB" in name or "FAB2RAM" in name):
                 continue
             self.writer.addPortVector(name, group[0], len(group[1])-1, indentLevel=2)