Merge pull request #110 from EverythingElseWasAlreadyTaken/WIP/setupt…

…ools

Build FABulous with setuptools

.github/workflows/fabric_gen.yml

@@ -11,15 +11,15 @@ jobs:
         runs-on: ubuntu-latest
 
         steps:
-            - uses: actions/checkout@v2
+            - uses: actions/checkout@v4
               with:
                   submodules: recursive
             - name: Set up Python 3.9
-              uses: actions/setup-python@v2
+              uses: actions/setup-python@v4
               with:
                   python-version: 3.9
             - name: Set up OSS CAD suite
-              uses: YosysHQ/setup-oss-cad-suite@v1
+              uses: YosysHQ/setup-oss-cad-suite@v2
             - name: Install dependencies
               run: |
                   python3 -m pip install --upgrade pip
@@ -31,15 +31,16 @@ jobs:
             - name: Lint with flake8
               run: |
                   # stop the build if there are Python syntax errors or undefined names
-                  flake8 fabric_generator/ --count --select=E9,F63,F7,F82 --show-source --statistics
+                  flake8 FABulous/**/*.py --count --select=E9,F63,F7,F82 --show-source --statistics
                   # exit-zero treats all errors as warnings. The GitHub editor is 127 chars wide
-                  flake8 fabric_generator --count --exit-zero --max-complexity=10 --max-line-length=127 --statistics
+                  flake8 FABulous/**/*.py --count --exit-zero --max-complexity=10 --max-line-length=127 --statistics
+            - name: Install FABulous
+              run: |
+                  pip3 install -e .
             - name: Run fabric generator flow
               run: |
-                  export FAB_ROOT=.
-                  python3.9 FABulous.py -c demo
-                  python3.9 FABulous.py demo --script ./demo/FABulous.tcl
-
+                  FABulous -c demo
+                  FABulous demo --script ./demo/FABulous.tcl
             - name: Run simulation smoketest
               run: |
                   cd ./demo/Test

.gitignore

@@ -1,2 +1,3 @@
 demo/
 **/__pycache__
+*.egg-info/

FABulous.py → FABulous/FABulous.py

@@ -1,3 +1,5 @@
+#!/usr/bin/env python
+
 # Copyright 2021 University of Manchester
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -14,48 +16,62 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-from contextlib import redirect_stdout
-from fabric_generator.utilities import genFabricObject, GetFabric
-import fabric_generator.model_generation_npnr as model_gen_npnr
-from fabric_generator.code_generation_VHDL import VHDLWriter
-from fabric_generator.code_generation_Verilog import VerilogWriter
-from FABulous_API import FABulous
+import argparse
+import cmd
 import csv
-from glob import glob
+import logging
 import os
-import argparse
 import pickle
+import platform
 import re
-import sys
-import subprocess as sp
-import shutil
-from typing import List, Literal
-import docker
-import cmd
 import readline
-import logging
+import shutil
+import subprocess as sp
+import sys
 import tkinter as tk
-from pathlib import PurePosixPath, PureWindowsPath
-import platform
 import traceback
+from contextlib import redirect_stdout
+from glob import glob
+from pathlib import PurePosixPath, PureWindowsPath
+from typing import List, Literal
+
+import docker
+import FABulous.fabric_generator.model_generation_npnr as model_gen_npnr
+from FABulous.fabric_generator.code_generation_Verilog import VerilogWriter
+from FABulous.fabric_generator.code_generation_VHDL import VHDLWriter
+from FABulous.fabric_generator.utilities import GetFabric, genFabricObject
+from FABulous.FABulous_API import FABulous
 
 readline.set_completer_delims(" \t\n")
 histfile = ""
 histfile_size = 1000
 
 MAX_BITBYTES = 16384
 
-fabulousRoot = os.getenv("FAB_ROOT")
-if fabulousRoot is None:
-    print("FAB_ROOT environment variable not set!")
-    print("Use 'export FAB_ROOT=<path to FABulous root>'")
-    sys.exit(-1)
-
 logger = logging.getLogger(__name__)
 logging.basicConfig(
     format="[%(levelname)s]-%(asctime)s - %(message)s", level=logging.INFO
 )
 
+metaDataDir = ".FABulous"
+
+fabulousRoot = os.getenv("FAB_ROOT")
+if fabulousRoot is None:
+    fabulousRoot = os.path.dirname(os.path.realpath(__file__))
+    logger.warning("FAB_ROOT environment variable not set!")
+    logger.warning(f"Using {fabulousRoot} as FAB_ROOT")
+else:
+    if not os.path.exists(fabulousRoot):
+        logger.error(
+            f"FAB_ROOT environment variable set to {fabulousRoot} but the directory does not exist"
+        )
+        sys.exit()
+    else:
+        if os.path.exists(f"{fabulousRoot}/FABulous"):
+            fabulousRoot = f"{fabulousRoot}/FABulous"
+
+    logger.info(f"FAB_ROOT set to {fabulousRoot}")
+
 
 # Create a FABulous Verilog project that contains all the required files
 def create_project(project_dir, type: Literal["verilog", "vhdl"] = "verilog"):
@@ -72,6 +88,11 @@ def create_project(project_dir, type: Literal["verilog", "vhdl"] = "verilog"):
         f"{project_dir}/",
         dirs_exist_ok=True,
     )
+    shutil.copytree(
+        f"{fabulousRoot}/fabric_cad/synth",
+        f"{project_dir}/Test/synth",
+        dirs_exist_ok=True,
+    )
 
     adjust_directory_in_verilog_tb(project_dir)
 
@@ -114,9 +135,7 @@ def adjust_directory_in_verilog_tb(project_dir):
         f"{fabulousRoot}/fabric_files/FABulous_project_template_verilog/Test/sequential_16bit_en_tb.v",
         "rt",
     ) as fin:
-        with open(
-            f"{fabulousRoot}/{project_dir}/Test/sequential_16bit_en_tb.v", "wt"
-        ) as fout:
+        with open(f"{project_dir}/Test/sequential_16bit_en_tb.v", "wt") as fout:
             for line in fin:
                 fout.write(line.replace("PROJECT_DIR", f"{project_dir}"))
 
@@ -161,8 +180,8 @@ class FABulousShell(cmd.Cmd):
 
 Type help or ? to list commands
 To see documentation for a command type:
-    help <command> 
-or 
+    help <command>
+or
     ?<command>
 
 To execute a shell command type:
@@ -974,8 +993,7 @@ def do_gen_bitStream_binary(self, args):
         logger.info(f"Generating Bitstream for design {self.projectDir}/{path}")
         logger.info(f"Outputting to {self.projectDir}/{parent}/{bitstream_file}")
         runCmd = [
-            "python3",
-            f"{fabulousRoot}/fabric_cad/bit_gen.py",
+            "bit_gen",
             "-genBitstream",
             f"{self.projectDir}/{parent}/{fasm_file}",
             f"{self.projectDir}/.FABulous/bitStreamSpec.bin",
@@ -1179,7 +1197,7 @@ def complete_tcl(self, text, *ignored):
         return self._complete_path(text)
 
 
-if __name__ == "__main__":
+def main():
     if sys.version_info < (3, 9, 0):
         print("Need Python 3.9 or above to run FABulous")
         exit(-1)
@@ -1232,7 +1250,6 @@ def complete_tcl(self, text, *ignored):
     args = parser.parse_args()
 
     args.top = args.project_dir.split("/")[-1]
-    metaDataDir = ".FABulous"
 
     if args.createProject:
         create_project(args.project_dir, args.writer)
@@ -1267,3 +1284,7 @@ def complete_tcl(self, text, *ignored):
                     fabShell.cmdloop()
         else:
             fabShell.cmdloop()
+
+
+if __name__ == "__main__":
+    main()

FABulous_API.py → FABulous/FABulous_API.py

@@ -1,14 +1,14 @@
-import fabric_generator.model_generation_vpr as model_gen_vpr
-import fabric_generator.model_generation_npnr as model_gen_npnr
-from fabric_generator.code_generation_VHDL import VHDLWriter
-import fabric_generator.code_generator as codeGen
-import fabric_generator.file_parser as fileParser
-from fabric_generator.fabric import Fabric, Tile
-from fabric_generator.fabric_gen import FabricGenerator
-from geometry_generator.geometry_gen import GeometryGenerator
-
 import logging
 
+import FABulous.fabric_generator.code_generator as codeGen
+import FABulous.fabric_generator.file_parser as fileParser
+import FABulous.fabric_generator.model_generation_npnr as model_gen_npnr
+import FABulous.fabric_generator.model_generation_vpr as model_gen_vpr
+from FABulous.fabric_generator.code_generation_VHDL import VHDLWriter
+from FABulous.fabric_generator.fabric import Fabric, Tile
+from FABulous.fabric_generator.fabric_gen import FabricGenerator
+from FABulous.geometry_generator.geometry_gen import GeometryGenerator
+
 logger = logging.getLogger(__name__)
 logging.basicConfig(
     format="[%(levelname)s]-%(asctime)s - %(message)s", level=logging.INFO

fabric_cad/bit_gen.py → FABulous/fabric_cad/bit_gen.py

@@ -1,14 +1,9 @@
-# Python 3
-from array import array
+#!/usr/bin/env python
+
+import pickle
 import re
 import sys
-from contextlib import redirect_stdout
-from io import StringIO
-import math
-import os
-import numpy
-import pickle
-import csv
+
 from fasm import *  # Remove this line if you do not have the fasm library installed and will not be generating a bitstream
 
 
@@ -260,39 +255,40 @@ def getTileAndWireByWireDest(self, loc: str, dest: str, jumps: bool = True):
 #####################################################################################
 # Main
 #####################################################################################
-
-# Strip arguments
-caseProcessedArguments = list(map(lambda x: x.strip(), sys.argv))
-processedArguments = list(map(lambda x: x.lower(), caseProcessedArguments))
-flagRE = re.compile("-\S*")
-
-if "-genBitstream".lower() in str(sys.argv).lower():
-    argIndex = processedArguments.index("-genBitstream".lower())
-
-    if len(processedArguments) <= argIndex + 3:
-        raise ValueError(
-            "\nError: -genBitstream expect three file names - the fasm file, the spec file and the output file"
-        )
-    elif (
-        flagRE.match(caseProcessedArguments[argIndex + 1])
-        or flagRE.match(caseProcessedArguments[argIndex + 2])
-        or flagRE.match(caseProcessedArguments[argIndex + 3])
-    ):
-        raise ValueError(
-            "\nError: -genBitstream expect three file names, but found a flag in the arguments:"
-            f" {caseProcessedArguments[argIndex + 1]}, {caseProcessedArguments[argIndex + 2]}, {caseProcessedArguments[argIndex + 3]}\n"
+def bit_gen():
+    # Strip arguments
+    caseProcessedArguments = list(map(lambda x: x.strip(), sys.argv))
+    processedArguments = list(map(lambda x: x.lower(), caseProcessedArguments))
+    flagRE = re.compile("-\S*")
+    if "-genBitstream".lower() in str(sys.argv).lower():
+        argIndex = processedArguments.index("-genBitstream".lower())
+        if len(processedArguments) <= argIndex + 3:
+            raise ValueError(
+                "\nError: -genBitstream expect three file names - the fasm file, the spec file and the output file"
+            )
+        elif (
+            flagRE.match(caseProcessedArguments[argIndex + 1])
+            or flagRE.match(caseProcessedArguments[argIndex + 2])
+            or flagRE.match(caseProcessedArguments[argIndex + 3])
+        ):
+            raise ValueError(
+                "\nError: -genBitstream expect three file names, but found a flag in the arguments:"
+                f" {caseProcessedArguments[argIndex + 1]}, {caseProcessedArguments[argIndex + 2]}, {caseProcessedArguments[argIndex + 3]}\n"
+            )
+
+        FasmFileName = caseProcessedArguments[argIndex + 1]
+        SpecFileName = caseProcessedArguments[argIndex + 2]
+        OutFileName = caseProcessedArguments[argIndex + 3]
+
+        genBitstream(FasmFileName, SpecFileName, OutFileName)
+
+    if ("-help".lower() in str(sys.argv).lower()) or ("-h" in str(sys.argv).lower()):
+        print("")
+        print("Options/Switches")
+        print(
+            "  -genBitstream foo.fasm spec.txt bitstream.txt - generates a bitstream - the first file is the fasm file, the second is the bitstream spec and the third is the fasm file to write to"
         )
 
-    FasmFileName = caseProcessedArguments[argIndex + 1]
-    SpecFileName = caseProcessedArguments[argIndex + 2]
-    OutFileName = caseProcessedArguments[argIndex + 3]
 
-    genBitstream(FasmFileName, SpecFileName, OutFileName)
-
-
-if ("-help".lower() in str(sys.argv).lower()) or ("-h" in str(sys.argv).lower()):
-    print("")
-    print("Options/Switches")
-    print(
-        "  -genBitstream foo.fasm spec.txt bitstream.txt - generates a bitstream - the first file is the fasm file, the second is the bitstream spec and the third is the fasm file to write to"
-    )
+if __name__ == "__main__":
+    bit_gen()

fabric_files/FABulous_project_template_verilog/Test/README.md → FABulous/fabric_files/FABulous_project_template_verilog/Test/README.md

@@ -1,4 +1,4 @@
-This assumes the default instructions were followed to build a 8x14 fabric in `../fabric_generator`.
+This assumes the default instructions were followed to build a 8x14 fabric in `../../fabric_generator`.
 
 Latest Yosys and `nextpnr-generic` from upstream (_not_ the old FABulous nextpnr fork) are used
 to build the test design.

fabric_files/FABulous_project_template_verilog/Test/build_test_design.sh → FABulous/fabric_files/FABulous_project_template_verilog/Test/build_test_design.sh

@@ -1,11 +1,11 @@
 #!/usr/bin/env bash
-SYNTH_TCL=../../fabric_cad/synth/synth_fabulous.tcl
-BIT_GEN=../../fabric_cad/bit_gen.py
+SYNTH_TCL=./synth/synth_fabulous.tcl
+BIT_GEN=bit_gen
 
 DESIGN=counter
 
 set -ex
 yosys -qp "tcl $SYNTH_TCL 4 top_wrapper test_design/${DESIGN}.json" test_design/${DESIGN}.v test_design/top_wrapper.v
 
 FAB_ROOT=.. nextpnr-generic --uarch fabulous --json test_design/${DESIGN}.json -o fasm=test_design/${DESIGN}_des.fasm
-python3 ${BIT_GEN} -genBitstream test_design/${DESIGN}_des.fasm ../.FABulous/bitStreamSpec.bin test_design/${DESIGN}.bin
+${BIT_GEN} -genBitstream test_design/${DESIGN}_des.fasm ../.FABulous/bitStreamSpec.bin test_design/${DESIGN}.bin

fabric_files/FABulous_project_template_verilog/Test/run_emulation_sim.sh → FABulous/fabric_files/FABulous_project_template_verilog/Test/run_emulation_sim.sh

@@ -1,17 +1,14 @@
 #!/usr/bin/env bash
 set -ex
 DESIGN=counter
-BITSTREAM=test_design/${DESIGN}.bin
-VERILOG=../../fabric_generator/verilog_output
-MAX_BITBYTES=16384
 
 rm -rf tmp
 mkdir tmp
 for i in $(find ../Tile -type f -name "*.v") $(find ../Fabric -type f -name "*.v")
-do 
+do
     cp $i tmp/
 done
 
-iverilog -D EMULATION -s fab_tb -o fab_tb.vvp test_design/${DESIGN}.vh tmp/* test_design/${DESIGN}.v fabulous_tb.v 
+iverilog -D EMULATION -s fab_tb -o fab_tb.vvp test_design/${DESIGN}.vh tmp/* test_design/${DESIGN}.v fabulous_tb.v
 vvp fab_tb.vvp
-rm -rf tmp
+rm -rf tmp

fabric_files/FABulous_project_template_verilog/Test/run_simulation.sh → FABulous/fabric_files/FABulous_project_template_verilog/Test/run_simulation.sh

@@ -2,17 +2,16 @@
 set -ex
 DESIGN=counter
 BITSTREAM=test_design/${DESIGN}.bin
-VERILOG=../../fabric_generator/verilog_output
 MAX_BITBYTES=16384
 
 rm -rf tmp
 mkdir tmp
 for i in $(find ../Tile -type f -name "*.v") $(find ../Fabric -type f -name "*.v")
-do 
+do
     cp $i tmp/
 done
 
-iverilog -s fab_tb -o fab_tb.vvp tmp/* test_design/${DESIGN}.v fabulous_tb.v 
+iverilog -s fab_tb -o fab_tb.vvp tmp/* test_design/${DESIGN}.v fabulous_tb.v
 python3 makehex.py $BITSTREAM $MAX_BITBYTES bitstream.hex
 vvp fab_tb.vvp
-rm -rf tmp
+rm -rf tmp