Skip to content

This project aims to provide an FPGA based NoC emulator to test and verify different mapping schedulings

License

Notifications You must be signed in to change notification settings

Nguyendien/NoC_FPGA_Emulator

 
 

Repository files navigation

NoC FPGA Emulator

Authors (in alphabetical order of last name):

  • Martin Dida
  • Nevin George
  • Vineeth Govind
  • Ranganathan Hariharan
  • Karl Janson
  • Apneet Kaur Sandhu
  • Behrad Niazmand
  • Siavoosh Payandeh Azad
  • René Pihlak
  • Tsotne Putkaradze
  • Jaan Raik
  • Hardi Selg

License: GNU GENERAL PUBLIC LICENSE Version 2

Copyright (C) 2015 as collective work. According to 17 U.S.C. 201(c) each author will retain their full ownership for their contribution.


In case you need something to be implemented please conact: siavoosh[AT]ati[DOT]ttu[DOT]ee maybe we can arrange it.


For ducmentations please refer to wiki!

Check our page at: http://siavooshpayandehazad.github.io/NoC_FPGA_Emulator

About

This project aims to provide an FPGA based NoC emulator to test and verify different mapping schedulings

Resources

License

Stars

Watchers

Forks

Packages

No packages published

Languages

  • VHDL 72.4%
  • C 16.7%
  • Verilog 7.2%
  • C++ 3.2%
  • Tcl 0.4%
  • Coq 0.1%