Merge pull request #1113 from Xilinx/2024.2.0

2024.2.0

.classpath

@@ -33,9 +33,9 @@
 	<classpathentry kind="lib" path="jars/kryo-5.2.1.jar"/>
 	<classpathentry kind="lib" path="jars/minlog-1.3.1.jar"/>
 	<classpathentry kind="lib" path="jars/jython-standalone-2.7.2.jar"/>
-	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.1.3.jar">
+	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.2.0.jar">
 		<attributes>
-			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.1.3-javadoc.jar!/"/>
+			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.2.0-javadoc.jar!/"/>
 		</attributes>
 	</classpathentry>
 	<classpathentry kind="lib" path="jars/jgrapht-core-1.3.0.jar"/>

.github/workflows/build.yml

@@ -5,7 +5,7 @@ on:
   pull_request:
 
 env:
-  RAPIDWRIGHT_VERSION: v2024.1.3-beta
+  RAPIDWRIGHT_VERSION: v2024.2.0-beta
 
 jobs:
   build:

RELEASE_NOTES.TXT

@@ -1,3 +1,62 @@
+============= RapidWright 2024.2.0-beta released on 2024-12-04 ================
+Notes: 
+  - Remove reliance on gap routing test (#1117)
+  - [ModuleInst] Fix placement behavior when requesting no overlaps (#1108)
+  - [RWRoute] Clock router for Versal architecture (#1102)
+  - Various preprocessing fixes for Versal routing (#1115)
+  - [CUFR] CUFR and PartialCUFR to default to --hus (#1111)
+  - [TestNet] Improve testSetPinsMultiSrcStatic to track many sources (#1082)
+  - Changes to support new array-based cell pin mappings (#1101)
+  - Update tests to reflect bug fixes and minor behavior changes (#1110)
+  - [RWRoute] Yet more cleanup (#1107)
+  - [RWRoute] Preserve nodes of Laguna sinks (#1104)
+  - [GlobalSignalRouting] routeStaticNets() to take a list of static pins (#1105)
+  - [RWRoute] Fix typo -- not an exclusive sink (#1106)
+  - [RWRoute] Versal optimizations (#1093)
+  - [RWRoute] RouteNode.setType() to accept any locals (#1103)
+  - [RWRoute] Further divide LOCAL nodes into EAST/WEST for UltraScale(+) (#1098)
+  - [Utils] isClocking() to include TileTypeEnum.CMT_L (#1100)
+  - TileGroup and DeviceBrowser Improvements (#1094)
+  - [RWRoute] Divide nodes into LOCAL and NON_LOCAL (#1095)
+  - Update actions and do not limit to 5G RAM (#1092)
+  - [HandPlacer] Cleanup snapping code in hand placer (#1091)
+  - [LUTTools] Add zero padding to LUT INIT strings (#1090)
+  - [NetTools] Add getNodeTrees() method and NodeTree class (#1089)
+  - [YosysTools] Add synthXilinx() wrapper for Yosys (#1086)
+  - [EDIFWriteLegalNameCache] busCollisionRenames to be a ConcurrentHashMap (#1088)
+  - Add ReportRouteStatus utility (#1087)
+  - [RWRoute] Signal router for Versal architecture (#1077)
+  - [FileTools] Add runCommand(String[] ...) & getExecutablePath(String) (#1085)
+  - [RouterHelper] findPathBetweenNodes() allow clocking if src/sink is so (#1083)
+  - [RouterHelper] projectOutputPinToINTNode() to breadth-first-search (#1081)
+  - [RouterHelper] projectInputPinToINTNode() to return solitary node (#1080)
+  - [RouterHelper] findPathBetweenNodes() to ignore clocking tiles (#1079)
+  - [RouterHelper] invertPossibleGndPinsToVccPins() to support Versal LUTs (#1078)
+  - [DesignTools] Fix createCeSrRstPinsToVCC() for US BRAMs (#1075)
+  - [DesignTools] Add LDCE/LDPE to types that need VCC (#1076)
+  - [NetTools] Add NetTools.isGlobalClock() (#1057)
+  - Static router for Versal architecture (#1073)
+  - [EDIFNetlist] getPhysicalPins() to call getPhysical{Gnd,Vcc}Pins() (#1074)
+  - Fix Null SLR References in Tiles in xcvp1902
+  - Add Implements Serializable to All RapidWright Classes
+  - [SiteInst] Improve memory usage of site routing using array instead of maps
+  - [Cell] Changes pin mappings from a map to an array to improve memory usage
+  - [BEL] Deprecate isSRIMR() in favour of more general isIMR()
+  - [Tile] Add getMaxUniqueAddress()
+  - [Net] Add support for multiple output sources
+
+API Additions:
+  - com.xilinx.rapidwright.design.Cell "public Pair<BELPin, String> getFirstPhysicalPinMapping()"
+  - com.xilinx.rapidwright.design.Cell "public int getUsedPhysicalPinsCount()"
+  - com.xilinx.rapidwright.design.Cell "public Set<String> getUsedPhysicalPins()"
+  - com.xilinx.rapidwright.design.Cell "public String[] getPhysicalPinMappings()"
+  - com.xilinx.rapidwright.design.Cell "public boolean usesPhysicalPin(String physicalPinName)"
+  - com.xilinx.rapidwright.design.Design "public boolean placeCell(Cell c, Site site, BEL bel, String[] physPinMappings)"
+  - com.xilinx.rapidwright.design.Net "public List<SitePinInst> getAlternateSources()"
+  - com.xilinx.rapidwright.device.BEL "public boolean isIMR()"
+  - com.xilinx.rapidwright.device.Tile "public int getMaxUniqueAddress()"
+
+
 ============= RapidWright 2024.1.3-beta released on 2024-10-02 ================
 Notes: 
   - [RWRoute] Further cleanup (#1070)

src/com/xilinx/rapidwright/design/DesignTools.java

@@ -289,7 +289,7 @@ public static ArrayList<BELPin> getCorrespondingBELInputPins(BELPin outputPin, S
                     Net net = inst.getNetFromSiteWire(siteWireName);
                     if (net == null) continue;
                     if (net.isStaticNet()) continue;
-                    if (!cell.getPinMappingsP2L().containsKey(pin.getName())) continue;
+                    if (!cell.usesPhysicalPin(pin.getName())) continue;
                     inputs.add(pin);
                 }
                 break;
@@ -325,7 +325,8 @@ public static ArrayList<BELPin> getCorrespondingBELOutputPins(BELPin inputPin, S
             if (net == null) continue;
             if (net.isStaticNet()) continue;
             if (net.getName().equals(Net.USED_NET)) continue;
-            if (!cell.getPinMappingsP2L().containsKey(pin.getName())) continue;
+            if (!cell.usesPhysicalPin(pin.getName()))
+                continue;
             outputs.add(pin);
         }
 
@@ -445,7 +446,7 @@ public static String invertLutInput (Cell lut, String physicalPinName) {
         long oldVal = new BigInteger(hexValueStr, 16).longValue();
         int numLutRows = Integer.parseInt(numLutRowsStr);
         int numInput = (int)(Math.log(numLutRows)/Math.log(2));
-        String logicalPinName = lut.getPinMappingsP2L().get(physicalPinName);
+        String logicalPinName = lut.getLogicalPinMapping(physicalPinName);
         int invertCol = getInvertCol(logicalPinName.substring(logicalPinName.length()-1));
         if (invertCol == -1) {
             System.err.println("Inverted Column is -1 is Function DesignTools.invertLutInput");
@@ -1563,12 +1564,11 @@ public static List<SitePinInst> unrouteCellPinSiteRouting(Cell cell, String logi
                             if (otherCell.isRoutethru()) {
                                 BELPin otherPin = null;
                                 if (pin.isOutput()) {
-                                    assert(otherCell.getPinMappingsP2L().size() == 1);
-                                    String otherPinName = otherCell.getPinMappingsP2L().keySet().iterator().next();
-                                    otherPin = pin.getBEL().getPin(otherPinName);
+                                    assert (otherCell.getUsedPhysicalPinsCount() == 1);
+                                    otherPin = otherCell.getFirstPhysicalPinMapping().getFirst();
                                 } else {
                                     // Make sure we are coming in on the routed-thru pin
-                                    String otherPinName = otherCell.getPinMappingsP2L().keySet().iterator().next();
+                                    String otherPinName = otherCell.getFirstPhysicalPinMapping().getFirst().getName();
                                     if (pin.getName().equals(otherPinName)) {
                                         otherPin = LUTTools.getLUTOutputPin(pin.getBEL());
                                     }
@@ -1777,7 +1777,8 @@ public static void makeBlackBox(Design d, EDIFHierCellInst hierarchicalCell) {
             }
 
             // Remove all physical nets first
-            for (String logPin : c.getPinMappingsP2L().values()) {
+            for (String logPin : c.getPhysicalPinMappings()) {
+                if (logPin == null) continue;
                 List<SitePinInst> removePins = unrouteCellPinSiteRouting(c, logPin);
                 for (SitePinInst pin : removePins) {
                     pinsToRemove.computeIfAbsent(pin.getNet(), $ -> new HashSet<>()).add(pin);
@@ -1971,7 +1972,7 @@ public static boolean stampPlacement(Design design, Module stamp, Map<String,Sit
                     }
 
                     Cell newCell = c.copyCell(newCellName, cellInst);
-                    design.placeCell(newCell, newSiteInst.getSite(), c.getBEL(), c.getPinMappingsP2L());
+                    design.placeCell(newCell, newSiteInst.getSite(), c.getBEL(), c.getPhysicalPinMappings());
                 }
 
                 for (SitePIP sitePIP : si.getUsedSitePIPs()) {
@@ -2306,8 +2307,8 @@ public static List<String> getAllRoutedSitePinsFromPhysicalPin(Cell cell, Net ne
                             }
                         } else {
                             if (possibleRouteThru.isRoutethru()) {
-                                String routeThru = possibleRouteThru.getPinMappingsP2L().keySet().iterator().next();
-                                queue.add(bel.getPin(routeThru));
+                                BELPin routeThru = possibleRouteThru.getFirstPhysicalPinMapping().getFirst();
+                                queue.add(routeThru);
                             }
                         }
                     }
@@ -3005,14 +3006,19 @@ private static void copySiteRouting(Cell copy, Cell orig, Map<String,String> src
         }
 
         EDIFHierCellInst cellInst = destNetlist.getHierCellInstFromName(copy.getName());
-        for (Entry<String,String> e : copy.getPinMappingsP2L().entrySet()) {
-            EDIFPortInst portInst = cellInst.getInst().getPortInst(e.getValue());
+        String[] physPinNames = copy.getPhysicalPinMappings();
+        for (int i = 0; i < physPinNames.length; i++) {
+            String logPinName = physPinNames[i];
+            if (logPinName == null) continue;
+            String physPinName = copy.getBEL().getPin(i).getName();
+
+            EDIFPortInst portInst = cellInst.getInst().getPortInst(logPinName);
             if (portInst == null) continue;
             EDIFNet edifNet = portInst.getNet();
 
             String netName = new EDIFHierNet(cellInst.getParent(), edifNet).getHierarchicalNetName();
 
-            String siteWireName = orig.getSiteWireNameFromPhysicalPin(e.getKey());
+            String siteWireName = orig.getSiteWireNameFromPhysicalPin(physPinName);
             Net origNet = origSiteInst.getNetFromSiteWire(siteWireName);
             if (origNet == null) continue;
             Net net = null;
@@ -3029,7 +3035,7 @@ private static void copySiteRouting(Cell copy, Cell orig, Map<String,String> src
                 }
             }
 
-            BELPin curr = copy.getBEL().getPin(e.getKey());
+            BELPin curr = copy.getBEL().getPin(physPinName);
             dstSiteInst.routeIntraSiteNet(net, curr, curr);
             boolean routingForward = curr.isOutput();
             Queue<BELPin> q = new LinkedList<BELPin>();
@@ -3068,7 +3074,7 @@ private static void copySiteRouting(Cell copy, Cell orig, Map<String,String> src
                             Cell rtCopy = tmpCell
                                     .copyCell(newCellName, tmpCell.getEDIFHierCellInst(), dstSiteInst);
                             dstSiteInst.getCellMap().put(belName, rtCopy);
-                            for (String belPinName : rtCopy.getPinMappingsP2L().keySet()) {
+                            for (String belPinName : rtCopy.getUsedPhysicalPins()) {
                                 BELPin tmp = rtCopy.getBEL().getPin(belPinName);
                                 if (tmp.isInput()) {
                                     curr = tmp;

src/com/xilinx/rapidwright/design/NetTools.java

@@ -144,4 +144,18 @@ public static List<NodeTree> getNodeTrees(Net net) {
 
         return subtrees;
     }
+
+    /**
+     * Checks if the provided net drives a clock site pin input.
+     * 
+     * @param net The net to examine.
+     * @return True if the net has a site pin clock input, false otherwise.
+     */
+    public static boolean hasClockSinks(Net net) {
+        for (SitePinInst sink : net.getPins()) { 
+            if (sink.isOutPin()) continue;
+            if (sink.getName().contains("CLK")) return true;
+        }
+        return false;
+    }
 }

src/com/xilinx/rapidwright/design/Unisim.java

@@ -33,12 +33,32 @@
 import com.xilinx.rapidwright.edif.EDIFLibrary;
 
 /**
- * Generated on: Wed May 01 19:57:08 MDT 2024
+ * Generated on: Thu Nov 21 13:34:09 MST 2024
  * by: com.xilinx.rapidwright.release.UnisimParser
  *
  * Enumerates supported Unisim primitives that map to Xilinx devices.
  */
 public enum Unisim {
+    AIE2PS_NOC_M_AXI,
+    AIE2PS_NOC_M_AXIS,
+    AIE2PS_NOC_S_AXI,
+    AIE2PS_NOC_S_AXIS,
+    AIE2PS_PL_M_AXIS128,
+    AIE2PS_PL_M_AXIS32,
+    AIE2PS_PL_M_AXIS64,
+    AIE2PS_PL_M_EVENTS,
+    AIE2PS_PL_S_AXIS128,
+    AIE2PS_PL_S_AXIS32,
+    AIE2PS_PL_S_AXIS64,
+    AIE2PS_PL_S_EVENTS,
+    AIE2P_PL_M_AXIS128,
+    AIE2P_PL_M_AXIS32,
+    AIE2P_PL_M_AXIS64,
+    AIE2P_PL_M_EVENTS,
+    AIE2P_PL_S_AXIS128,
+    AIE2P_PL_S_AXIS32,
+    AIE2P_PL_S_AXIS64,
+    AIE2P_PL_S_EVENTS,
     AIE_ML_NOC_M_AXI,
     AIE_ML_NOC_M_AXIS,
     AIE_ML_NOC_S_AXI,
@@ -85,6 +105,8 @@ public enum Unisim {
     AND5B4,
     AND5B5,
     AUTOBUF,
+    AXI32,
+    BFR_FT,
     BFR_MATMULX,
     BIBUF,
     BITSLICE_CONTROL,
@@ -157,8 +179,10 @@ public enum Unisim {
     DDRMC,
     DDRMC5,
     DDRMC5C,
+    DDRMC5E,
     DDRMC_RIU,
     DFE_CFR,
+    DFE_CHANNELIZER,
     DFE_DUC_DDC,
     DFE_FFT,
     DFE_FIR,
@@ -258,6 +282,7 @@ public enum Unisim {
     FRAME_ECCE3,
     FRAME_ECCE4,
     FRAME_ECC_VIRTEX6,
+    FUSE_CLK,
     GND,
     GTF_CHANNEL,
     GTF_COMMON,
@@ -769,6 +794,7 @@ public enum Unisim {
     NOC2_NMU256,
     NOC2_NMU512,
     NOC2_NPS5555,
+    NOC2_NPS6X,
     NOC2_NPS7575,
     NOC2_NSU128,
     NOC2_NSU256,
@@ -1193,6 +1219,7 @@ public enum Unisim {
     PLLE4_BASE,
     PLL_ADV,
     PLL_BASE,
+    PS11,
     PS7,
     PS8,
     PS9,
@@ -1290,9 +1317,11 @@ public enum Unisim {
     RAMS64E1,
     RAMS64E5,
     RFADC,
+    RFADCE5,
     RFADC_13B4W_M0,
     RFADC_13B4W_M1,
     RFDAC,
+    RFDACE5,
     RIU_OR,
     ROM128X1,
     ROM16X1,
@@ -1301,8 +1330,10 @@ public enum Unisim {
     ROM64X1,
     RXTX_BITSLICE,
     RX_BITSLICE,
+    SDFEC_LD,
     SIM_CONFIGE2,
     SIM_CONFIGE3,
+    SIM_CONFIGE4,
     SRL16,
     SRL16E,
     SRL16E_1,

src/com/xilinx/rapidwright/design/tools/LUTTools.java

@@ -390,9 +390,9 @@ public static EDIFPropertyValue configureLUT(EDIFCellInst c, String equation) {
      */
     public static String getLUTEquation(Cell c) {
         if (c.isRoutethru()) {
-            Set<Entry<String, String>> entrySet = c.getPinMappingsP2L().entrySet();
-            assert (entrySet.size() == 1);
-            return "O" + c.getBELName().charAt(1) + "=" + entrySet.iterator().next().getKey();
+            BELPin rtEntry = c.getFirstPhysicalPinMapping().getFirst();
+            assert (c.getUsedPhysicalPinsCount() == 1);
+            return "O" + c.getBELName().charAt(1) + "=" + rtEntry.getName();
         }
         return getLUTEquation(c.getEDIFCellInst());
     }

src/com/xilinx/rapidwright/design/tools/RelocationTools.java

@@ -39,6 +39,7 @@
 import com.xilinx.rapidwright.design.DesignTools;
 import com.xilinx.rapidwright.design.Module;
 import com.xilinx.rapidwright.design.Net;
+import com.xilinx.rapidwright.design.NetTools;
 import com.xilinx.rapidwright.design.SiteInst;
 import com.xilinx.rapidwright.design.SitePinInst;
 import com.xilinx.rapidwright.design.blocks.PBlock;
@@ -284,7 +285,7 @@ public static boolean relocate(Design design,
                 }
             }
 
-            boolean isClockNet = n.isClockNet() || n.hasGapRouting();
+            boolean isClockNet = n.isClockNet() || NetTools.hasClockSinks(n);
             n.getPIPs().removeIf((sp) -> {
                 Tile st = sp.getTile();
                 Tile dt = st.getTileXYNeighbor(tileColOffset, tileRowOffset);

src/com/xilinx/rapidwright/device/FamilyType.java

@@ -27,7 +27,7 @@
 
 
 /**
- * Generated on: Wed May 01 19:03:12 MDT 2024
+ * Generated on: Thu Nov 21 13:06:39 MST 2024
  * by: com.xilinx.rapidwright.release.PartNamePopulator
  *
  * Set of all Supported Xilinx families in RapidWright
@@ -54,7 +54,9 @@ public enum FamilyType {
         QKINTEXUPLUS,
         QRKINTEXU,
         QRVERSALAICORE,
+        QRVERSALAIEDGE,
         QVERSALAICORE,
+        QVERSALAIEDGE,
         QVERSALPREMIUM,
         QVERSALPRIME,
         QVIRTEX7,

src/com/xilinx/rapidwright/device/IOBankType.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Advanced Micro Devices, Inc.
@@ -27,7 +27,7 @@
 
 
 /**
- * Generated on: Wed May 17 23:03:43 2023
+ * Generated on: Thu Nov 21 13:34:08 MST 2024
  * by: com.xilinx.rapidwright.release.SiteAndTileTypeUpdater
  *
  * Enumeration of IOBankType type for all valid devices within Vivado.
@@ -41,5 +41,7 @@ public enum IOBankType {
     BT_MGT,
     BT_NO_USER_IO,
     BT_PSS,
+    BT_X5,
+    BT_X5IO,
     BT_XP,
 }