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Remove vsim/emulator flows, add simple make verilog flow (backport #3494) #3502

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merged 1 commit into from
Sep 26, 2023
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Remove vsim/emulator flows, add simple make verilog flow (backport #3494) #3502

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14 changes: 14 additions & 0 deletions Makefile
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Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
base_dir=$(abspath ./)

CHISEL_VERSION=3.6.0
MODEL ?= TestHarness
PROJECT ?= freechips.rocketchip.system
CFG_PROJECT ?= $(PROJECT)
CONFIG ?= $(CFG_PROJECT).DefaultConfig
MILL ?= mill

verilog:
cd $(base_dir) && $(MILL) emulator[freechips.rocketchip.system.TestHarness,$(CONFIG)].mfccompiler.compile

clean:
rm -rf out/
76 changes: 0 additions & 76 deletions Makefrag
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