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wirelength_analyzer.yml
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[GHA] Fix net_printer workflow to have correct parent net names (#57) wirelength_analyzer #91: Commit 0626222 pushed by pull bot
January 7, 2024 01:02 2m 56s master
master
January 7, 2024 01:02 2m 56s
[pull] master from Xilinx:master wirelength_analyzer #90: Pull request #16 opened by pull bot
January 6, 2024 16:03 2m 55s Xilinx:master
Xilinx:master
January 6, 2024 16:03 2m 55s
Move numDiffs out wirelength_analyzer #89: Commit eaccc26 pushed by eddieh-xlnx
January 4, 2024 19:48 2m 46s design_diff
design_diff
January 4, 2024 19:48 2m 46s
Skip CheckPhysNetlist's DesignComparator for koios as out of memory wirelength_analyzer #88: Commit 13f4470 pushed by eddieh-xlnx
January 4, 2024 19:45 2m 51s design_diff
design_diff
January 4, 2024 19:45 2m 51s
Check for presence of no diffs found wirelength_analyzer #87: Commit c1fa27c pushed by eddieh-xlnx
January 4, 2024 19:15 2m 55s design_diff
design_diff
January 4, 2024 19:15 2m 55s
Update GitHub Actions to check for no non-PIP diffs wirelength_analyzer #86: Commit d19fc79 pushed by eddieh-xlnx
January 4, 2024 19:07 2m 58s design_diff
design_diff
January 4, 2024 19:07 2m 58s
[NXRoute] Eliminate route conflicts with pre-routed nets (#55) wirelength_analyzer #85: Commit 1f8fcc6 pushed by pull bot
January 4, 2024 10:05 3m 11s master
master
January 4, 2024 10:05 3m 11s
[pull] master from Xilinx:master wirelength_analyzer #84: Pull request #15 opened by pull bot
January 4, 2024 01:04 3m 5s Xilinx:master
Xilinx:master
January 4, 2024 01:04 3m 5s
Restore BENCHMARKS_URL wirelength_analyzer #83: Commit 918cb5a pushed by eddieh-xlnx
December 23, 2023 23:34 2m 53s master
master
December 23, 2023 23:34 2m 53s
Update RapidWright submodule wirelength_analyzer #82: Commit 8d54f7c pushed by eddieh-xlnx
December 23, 2023 22:33 2m 55s physnetwriter_padout
physnetwriter_padout
December 23, 2023 22:33 2m 55s
Fix net_printer workflow wirelength_analyzer #81: Commit ab7c8ff pushed by eddieh-xlnx
December 23, 2023 21:05 3m 19s physnetwriter_padout
physnetwriter_padout
December 23, 2023 21:05 3m 19s
Fix net_printer workflow wirelength_analyzer #80: Commit 14c7540 pushed by eddieh-xlnx
December 22, 2023 20:07 2m 53s physnetwriter_padout
physnetwriter_padout
December 22, 2023 20:07 2m 53s
Double quotes? wirelength_analyzer #79: Commit b26edab pushed by eddieh-xlnx
December 22, 2023 20:03 2m 48s physnetwriter_padout
physnetwriter_padout
December 22, 2023 20:03 2m 48s
Double dollar? wirelength_analyzer #78: Commit f6ff1c1 pushed by eddieh-xlnx
December 22, 2023 19:58 6m 55s physnetwriter_padout
physnetwriter_padout
December 22, 2023 19:58 6m 55s
Print GND/VCC stubs in GHA wirelength_analyzer #77: Commit 9cc0db9 pushed by eddieh-xlnx
December 22, 2023 19:53 3m 1s physnetwriter_padout
physnetwriter_padout
December 22, 2023 19:53 3m 1s
[wirelength_analyzer] Add support for DIFFINBUF (#52) wirelength_analyzer #76: Commit b418ed8 pushed by pull bot
December 22, 2023 15:01 2m 57s master
master
December 22, 2023 15:01 2m 57s
[pull] master from Xilinx:master wirelength_analyzer #75: Pull request #14 opened by pull bot
December 22, 2023 05:43 2m 59s Xilinx:master
Xilinx:master
December 22, 2023 05:43 2m 59s
Switch over to temp URL wirelength_analyzer #74: Commit 81e295c pushed by eddieh-xlnx
December 20, 2023 05:34 3m 0s physnetwriter_padout
physnetwriter_padout
December 20, 2023 05:34 3m 0s
Fix wirelength_analyzer when terminating at a comb cell (e.g. LUT) (#50) wirelength_analyzer #73: Commit e8e0ee8 pushed by pull bot
December 15, 2023 04:14 3m 4s master
master
December 15, 2023 04:14 3m 4s
[pull] master from Xilinx:master wirelength_analyzer #72: Pull request #13 opened by pull bot
December 15, 2023 00:29 2m 54s Xilinx:master
Xilinx:master
December 15, 2023 00:29 2m 54s
Try wirelength_analyzer #71: Commit 07b1173 pushed by eddieh-xlnx
December 12, 2023 17:55 2m 51s wa
wa
December 12, 2023 17:55 2m 51s
Restore official BENCHMARKS_URL wirelength_analyzer #70: Commit da8f1a1 pushed by pull bot
December 6, 2023 19:05 2m 56s master
master
December 6, 2023 19:05 2m 56s
[pull] master from Xilinx:master wirelength_analyzer #69: Pull request #12 opened by pull bot
December 6, 2023 10:05 3m 9s Xilinx:master
Xilinx:master
December 6, 2023 10:05 3m 9s
OUTBUF -> OBUFT wirelength_analyzer #68: Commit f1816b6 pushed by eddieh-xlnx
December 5, 2023 20:20 2m 56s fix_corundum
fix_corundum
December 5, 2023 20:20 2m 56s
Add OUTBUF too wirelength_analyzer #67: Commit 889e8ca pushed by eddieh-xlnx
December 5, 2023 20:09 3m 41s fix_corundum
fix_corundum
December 5, 2023 20:09 3m 41s