[pull] master from Xilinx:master

.github/workflows/make.yml

@@ -1,4 +1,4 @@
-# Copyright (C) 2023, Advanced Micro Devices, Inc.  All rights reserved.
+# Copyright (C) 2024, Advanced Micro Devices, Inc.  All rights reserved.
 #
 # Author: Eddie Hung, AMD
 #
@@ -18,14 +18,19 @@ jobs:
         router:
           - rwroute
           - nxroute-poc
-        lutpinswap:
+        lutpinswapping:
+          - false
+          - true
+        lutroutethru:
           - false
           - true
         benchmark:
+          - logicnets_jscl
           - boom_med_pb
           - vtr_mcml
           - rosetta_fd
           - corundum_25g
+          - finn_radioml
           - vtr_lu64peeng
           - corescore_500
           - corescore_500_pb
@@ -45,7 +50,10 @@ jobs:
             benchmark: ispd16_example2
           # NXRoute does not support LUT pin swapping
           - router: nxroute-poc
-            lutpinswap: true
+            lutpinswapping: true
+          # NXRoute does not support LUT routethrus
+          - router: nxroute-poc
+            lutroutethru: true
     steps:
       - uses: actions/checkout@v3
         with:
@@ -70,7 +78,8 @@ jobs:
           # For certain benchmarks, wirelength_analyzer/CheckPhysNetlist requires more memory than that available in GitHub Actions
           WIRELENGTH_ANALYZER_MOCK_RESULT: ${{ matrix.benchmark == 'koios_dla_like_large' }}
           CHECK_PHYS_NETLIST_DIFF_MOCK_RESULT: ${{ matrix.benchmark == 'koios_dla_like_large' }}
-          RWROUTE_FORCE_LUT_PIN_SWAP:   ${{ matrix.router == 'rwroute' && matrix.lutpinswap }}
+          RWROUTE_FORCE_LUT_PINSWAPPING: ${{ matrix.router == 'rwroute' && matrix.lutpinswapping }}
+          RWROUTE_FORCE_LUT_ROUTETHRU:   ${{ matrix.router == 'rwroute' && matrix.lutroutethru }}
         run: |
           make ROUTER="${{ matrix.router }}" BENCHMARKS="${{ matrix.benchmark }}" VERBOSE=1
       - name: Score summary
@@ -113,7 +122,7 @@ jobs:
       - uses: actions/upload-artifact@v3
         if: always()
         with:
-          name: ${{ matrix.router }}${{ matrix.router == 'rwroute' && matrix.lutpinswap && '-lutpinswap' || ''}}-${{ matrix.benchmark }}
+          name: ${{ matrix.router }}${{ matrix.router == 'rwroute' && matrix.lutpinswapping && '-lutpinswapping' || ''}}${{ matrix.router == 'rwroute' && matrix.lutroutethru && '-lutroutethru' || ''}}-${{ matrix.benchmark }}
           path: |
            *.dcp
            *.phys

.github/workflows/net_printer.yml

@@ -1,4 +1,4 @@
-# Copyright (C) 2023, Advanced Micro Devices, Inc.  All rights reserved.
+# Copyright (C) 2024, Advanced Micro Devices, Inc.  All rights reserved.
 #
 # Author: Eddie Hung, AMD
 #
@@ -16,10 +16,12 @@ jobs:
       fail-fast: false
       matrix:
         benchmark:
+          - logicnets_jscl
           - boom_med_pb
           - vtr_mcml
           - rosetta_fd
           - corundum_25g
+          - finn_radioml
           - vtr_lu64peeng
           - corescore_500
           - corescore_500_pb
@@ -49,6 +51,10 @@ jobs:
       - name: Print VCC stubs
         run: |
           sed -n -e '/Stub: 0/,$p' vcc.physnet
+      - name: Print global nets (boom_med_pb)
+        if: matrix.benchmark == 'boom_med_pb'
+        run:
+          python3 net_printer/np.py ${{ matrix.benchmark }}_unrouted.phys clock_uncore_clock_IBUF_BUFG system/prci_ctrl_domain/resetSynchronizer/x1_member_allClocks_uncore_reset_catcher/io_sync_reset_chain/output_chain/sync_0_reg_0
       - name: Print largest global net (corundum_25g)
         if: matrix.benchmark == 'corundum_25g'
         run:

Makefile

@@ -1,4 +1,4 @@
-# Copyright (C) 2023, Advanced Micro Devices, Inc.  All rights reserved.
+# Copyright (C) 2024, Advanced Micro Devices, Inc.  All rights reserved.
 #
 # Author: Eddie Hung, AMD
 #
@@ -8,10 +8,12 @@
 SHELL := /bin/bash -o pipefail
 
 # List of all benchmarks (default to all)
-BENCHMARKS ?= boom_med_pb		\
+BENCHMARKS ?= logicnets_jscl		\
+              boom_med_pb		\
               vtr_mcml			\
               rosetta_fd		\
               corundum_25g		\
+              finn_radioml		\
               vtr_lu64peeng		\
               corescore_500		\
               corescore_500_pb		\
@@ -21,7 +23,7 @@ BENCHMARKS ?= boom_med_pb		\
               ispd16_example2
 
 
-BENCHMARKS_URL = https://github.com/eddieh-xlnx/fpga24_routing_contest/releases/download/benchmarks/benchmarks.tar.gz
+BENCHMARKS_URL = https://github.com/Xilinx/fpga24_routing_contest/releases/latest/download/benchmarks.tar.gz
 
 # Inherit proxy settings from the host if they exist
 HTTPHOST=$(firstword $(subst :, ,$(subst http:,,$(subst /,,$(HTTP_PROXY)))))
@@ -65,7 +67,7 @@ run-$(ROUTER): score-$(ROUTER)
 # Also download/generate all device files necessary for the xcvu3p device
 .PHONY: compile-java
 compile-java:
-	./gradlew $(JAVA_PROXY) compileJava
+	_JAVA_OPTIONS="$(JAVA_PROXY)" ./gradlew compileJava
 	_JAVA_OPTIONS="$(JAVA_PROXY)" RapidWright/bin/rapidwright Jython -c "FileTools.ensureDataFilesAreStaticInstallFriendly('xcvu3p')"
 
 .PHONY: install-python-deps
@@ -91,7 +93,7 @@ fpga-interchange-schema/interchange/capnp/java.capnp:
 # $^ (%.netlist and %_rwroute.phys), and display/redirect all output to [email protected] (%_rwroute.check.log).
 # The exit code of Gradle determines if 'PASS' or 'FAIL' is written to $@ (%_rwroute.check)
 %_$(ROUTER).check: %.netlist %_$(ROUTER).phys %_unrouted.phys | compile-java
-	if ./gradlew -DjvmArgs="-Xms6g -Xmx6g" -Dmain=com.xilinx.fpga24_routing_contest.CheckPhysNetlist :run --args='$^' $(call log_and_or_display,[email protected]); then \
+	if ./gradlew --offline -DjvmArgs="-Xms6g -Xmx6g" -Dmain=com.xilinx.fpga24_routing_contest.CheckPhysNetlist :run --args='$^' $(call log_and_or_display,[email protected]); then \
             echo "PASS" > $@; \
         else \
             echo "FAIL" > $@; \
@@ -130,13 +132,14 @@ distclean: clean
 # Gradle is used to invoke the PartialRouterPhysNetlist class' main method with arguments
 # $< (%_unrouted.phys) and $@ (%_rwroute.phys), and display/redirect all output into %_rwroute.phys.log
 %_rwroute.phys: %_unrouted.phys | compile-java
-	(/usr/bin/time ./gradlew -DjvmArgs="$(JVM_HEAP)" -Dmain=com.xilinx.fpga24_routing_contest.PartialRouterPhysNetlist :run --args='$< $@') $(call log_and_or_display,[email protected])
+	(/usr/bin/time ./gradlew --offline -DjvmArgs="$(JVM_HEAP)" -Dmain=com.xilinx.fpga24_routing_contest.PartialRouterPhysNetlist :run --args='$< $@') $(call log_and_or_display,[email protected])
 
 ## NXROUTE-POC
 %_nxroute-poc.phys: %_unrouted.phys xcvu3p.device | install-python-deps fpga-interchange-schema/interchange/capnp/java.capnp
 	(/usr/bin/time python3 networkx-proof-of-concept-router/nxroute-poc.py $< $@) $(call log_and_or_display,[email protected])
 
 ## EXAMPLEROUTE
+## (please only modify '<custom router here>' to ensure that all contest infrastructure remains in place)
 # %_exampleroute.phys: %_unrouted.phys
 # 	(/usr/bin/time <custom router here> $< $@) $(call log_and_or_display,[email protected])
 
@@ -146,8 +149,8 @@ distclean: clean
 
 # Required Apptainer args:
 # --pid: ensures all processes apptainer spawns are killed with the container
-# --home `pwd`: overrides the home directory inside the container to be the current dir
-APPTAINER_RUN_ARGS = --pid --home `pwd`
+# --home: overrides the home directory bound into the container to be the 'fakehome' subdir
+APPTAINER_RUN_ARGS = --pid --home `pwd`/fakehome
 ifneq ($(wildcard /tools),)
     # Creates a read-only mount of the host system's `/tools` directory to the container's
     # /tools` directory, which allows the container to access the host Vivado installation
@@ -165,14 +168,21 @@ endif
 %_container.sif: alpha_submission/%_container.def
 	apptainer build $@ $<
 
+fakehome:
+	mkdir fakehome
+
 # Use the <ROUTER>_container.sif Apptainer image to run all benchmarks
 .PHONY: run-container
-run-container: $(ROUTER)_container.sif
+run-container: $(ROUTER)_container.sif | fakehome
+	# Clear out the fakehome subdirectory
+	rm -rf fakehome/* fakehome/.*
 	apptainer exec $(APPTAINER_RUN_ARGS) $< make ROUTER="$(ROUTER)" BENCHMARKS="$(BENCHMARKS)" VERBOSE="$(VERBOSE)"
 
 # Use the <ROUTER>_container.sif Apptainer image to run a single small benchmark for testing
-.PHONY: test-container
+.PHONY: test-container | fakehome
 test-container: $(ROUTER)_container.sif
+	# Clear out the fakehome subdirectory
+	rm -rf fakehome/* fakehome/.*
 	apptainer exec $(APPTAINER_RUN_ARGS) $< make ROUTER="$(ROUTER)" BENCHMARKS="boom_med_pb" VERBOSE="$(VERBOSE)"
 
 SUBMISSION_NAME = $(ROUTER)_submission_$(shell date +%Y%m%d%H%M%S)

README.md

@@ -15,3 +15,4 @@ Utilities:
 * [`net_printer`](https://github.com/Xilinx/fpga24_routing_contest/tree/master/net_printer) -- inspect the routing of nets in a Physical Netlist.
 * [`DcpToFPGAIF`](https://github.com/Xilinx/fpga24_routing_contest/pull/10) -- process a DCP into FPGAIF Logical and Physical Netlists for use with this contest.
 * [`wirelength_analyzer`](https://github.com/Xilinx/fpga24_routing_contest/tree/master/wirelength_analyzer) -- compute a [critical-path wirelength](https://xilinx.github.io/fpga24_routing_contest/score.html#critical-path-wirelength) for a routed FPGAIF Physical Netlist.
+* [`DiffPhysNetlist`](https://github.com/Xilinx/fpga24_routing_contest/pull/66) -- display any placement/intra-site routing differences between two FPGAIF Physical Netlists.

docs/benchmarks.md

@@ -7,10 +7,12 @@ table:
 
 |Source Benchmark Suite|Benchmark Name|LUTs|FFs|DSPs|BRAMs|OOC [1]|
 |----------------------|--------------|----|---|----|-----|-------|
-| [BOOM](https://docs.boom-core.org/en/latest/sections/intro-overview/boom.html)                                          |`med_pb` (MediumBoomConfig with area constraint)   |36k |17k |24  |142|Y   |
+| [LogicNets](https://github.com/Xilinx/logicnets)                                                                        |`jscl` (Jet Substructure Classification L)         |31k |2k  |0   |0  |Y   |
+| [BOOM](https://docs.boom-core.org/en/latest/sections/intro-overview/boom.html)                                          |`med_pb` (MediumBoomConfig with area constraint)   |36k |17k |24  |142|N   |
 | [VTR](https://docs.verilogtorouting.org/en/latest/vtr/benchmarks/#vtr-benchmarks)                                       |`mcml`                                             |43k |15k |105 |142|Y   |
 | [Rosetta](https://github.com/cornell-zhang/rosetta)                                                                     |`fd` (face-detection)                              |46k |39k |72  |62 |Y   |
-| [Corundum](https://github.com/corundum/corundum)                                                                        |`25g` (ADM_PCIE_9V3 25G)                           |73k |96k |0   |221|Y   |
+| [Corundum](https://github.com/corundum/corundum)                                                                        |`25g` (ADM_PCIE_9V3 25G)                           |73k |96k |0   |221|N   |
+| [FINN](https://github.com/Xilinx/finn)                                                                                  |`radioml`                                          |74k |46k |0   |25 |Y   |
 | [VTR](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/benchmarks/verilog/LU64PEEng.v) |`lu64peeng`                                        |90k |36k |128 |303|Y   |
 | [CoreScore](https://github.com/olofk/corescore)                                                                         |`500` (500 SERV cores)                             |96k |116k|0   |250|N   |
 | [CoreScore](https://github.com/olofk/corescore)                                                                         |`500_pb` (500 SERV cores with area constraint)     |96k |116k|0   |250|N   |

docs/contact.md

@@ -8,3 +8,12 @@ For all enquiries, please contact [[email protected]](mailto:[email protected]
 * Chris Lavin
 * Zak Nafziger
 * Alireza Kaviani
+
+## Acknowledgements
+
+The organizers are grateful to the following people for their help in the development of this contest:
+
+- Nicholas Fraser (AMD)
+- Jakoba Petri-Koenig (AMD)
+- Thomas Preusser (AMD)
+- Shashwat Shrivastava (EPFL)

src/com/xilinx/fpga24_routing_contest/CheckPhysNetlist.java

@@ -58,7 +58,7 @@ public static void main(String[] args) throws IOException, InterruptedException
         // Read the routed and unrouted Physical Netlists
         Design routedDesign = PhysNetlistReader.readPhysNetlist(args[1]);
         int numDiffs = 0;
-        if (System.getenv("CHECK_PHYS_NETLIST_DIFF_MOCK_RESULT").equals("true")) {
+        if ("true".equals(System.getenv("CHECK_PHYS_NETLIST_DIFF_MOCK_RESULT"))) {
             System.out.println("::warning file=" + args[1] + "::CheckPhysNetlist's DesignComparator not run because CHECK_PHYS_NETLIST_DIFF_MOCK_RESULT is set");
         } else {
             Design unroutedDesign = PhysNetlistReader.readPhysNetlist(args[2]);

src/com/xilinx/fpga24_routing_contest/DiffPhysNetlist.java

@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.  All rights reserved.
+ *
+ * Author: Eddie Hung, AMD
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+package com.xilinx.fpga24_routing_contest;
+
+import com.xilinx.rapidwright.design.Design;
+import com.xilinx.rapidwright.design.compare.DesignComparator;
+import com.xilinx.rapidwright.interchange.PhysNetlistReader;
+
+import java.io.IOException;
+
+public class DiffPhysNetlist {
+    public static void main(String[] args) throws IOException {
+        if (args.length != 2) {
+            System.err.println("USAGE: <routed.phys> <unrouted.phys>");
+            return;
+        }
+
+        // Disable verbose Physical Netlist checks
+        PhysNetlistReader.CHECK_CONSTANT_ROUTING_AND_NET_NAMING = false;
+        PhysNetlistReader.CHECK_AND_CREATE_LOGICAL_CELL_IF_NOT_PRESENT = false;
+        PhysNetlistReader.VALIDATE_MACROS_PLACED_FULLY = false;
+        PhysNetlistReader.CHECK_MACROS_CONSISTENT = false;
+
+        // Read the routed and unrouted Physical Netlists
+        Design routedDesign = PhysNetlistReader.readPhysNetlist(args[0]);
+        Design unroutedDesign = PhysNetlistReader.readPhysNetlist(args[1]);
+
+        DesignComparator dc = new DesignComparator();
+        // Only compare PIPs on static and clock nets
+        dc.setComparePIPs((net) -> net.isStaticNet() || net.isClockNet());
+        int numDiffs = dc.compareDesigns(unroutedDesign, routedDesign);
+        if (numDiffs == 0) {
+            System.out.println("INFO: No differences found between routed and unrouted netlists");
+        } else {
+            dc.printDiffReport(System.out);
+        }
+
+        System.exit(numDiffs == 0 ? 0 : 1);
+    }
+}
+

src/com/xilinx/fpga24_routing_contest/PartialRouterPhysNetlist.java

@@ -63,14 +63,24 @@ public static void main(String[] args) throws IOException {
         routerArgs.addAll(List.of("--initialPresentCongestionFactor", "0.5"));
         routerArgs.addAll(List.of("--presentCongestionMultiplier", "2"));
         routerArgs.addAll(List.of("--historicalCongestionFactor", "1"));
-        // Optionally, enable LUT pin swapping where all inputs of a LUT are considered
-        // to be equivalent
+
+        // Optionally, allow RWRoute to perform LUT pin swapping such that all LUT input sinks
+        // are considered to be equivalent
         //routerArgs.add("--lutPinSwapping");
 
-        if (System.getenv().getOrDefault("RWROUTE_FORCE_LUT_PIN_SWAP", "false").equals("true")) {
-            // For testing purposes
+        // Optionally, allow RWRoute to consider LUT routethrus, where unused LUT resources
+        // (subject to a number of constraints) can be repurposed as an additional routing
+        // resource
+        //routerArgs.add("--lutRoutethru");
+
+        // Primarily for testing purposes
+        if (System.getenv().getOrDefault("RWROUTE_FORCE_LUT_PINSWAPPING", "false").equals("true")) {
             routerArgs.add("--lutPinSwapping");
-	}
+        }
+        if (System.getenv().getOrDefault("RWROUTE_FORCE_LUT_ROUTETHRU", "false").equals("true")) {
+            routerArgs.add("--lutRoutethru");
+        }
+
         if (routerArgs.contains("--lutPinSwapping")) {
             // Ask RWRoute not to perform any intra-site routing updates to reflect
             // any LUT pin swapping that occurs during routing, to fulfill the