bench: c4 initialize vars to zero in order to get same behavior in Ve…

…rilator and iVerilog
ekiwi · Jan 5, 2024 · 67cca6c · 67cca6c
1 parent abeda8b
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Showing 3 changed files with 26 additions and 7 deletions.
diff --git a/benchmarks/fpga-debugging/axis-async-fifo-c4/axis_register.v b/benchmarks/fpga-debugging/axis-async-fifo-c4/axis_register.v
@@ -95,7 +95,7 @@ if (REG_TYPE > 1) begin
     reg [DATA_WIDTH-1:0] m_axis_tdata_reg  = {DATA_WIDTH{1'b0}};
     reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg  = {KEEP_WIDTH{1'b0}};
     reg                  m_axis_tvalid_reg = 1'b0;
-    reg                  m_axis_tvalid_next;
+    reg                  m_axis_tvalid_next = 0;
     reg                  m_axis_tlast_reg  = 1'b0;
     reg [ID_WIDTH-1:0]   m_axis_tid_reg    = {ID_WIDTH{1'b0}};
     reg [DEST_WIDTH-1:0] m_axis_tdest_reg  = {DEST_WIDTH{1'b0}};
@@ -104,16 +104,16 @@ if (REG_TYPE > 1) begin
     reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg  = {DATA_WIDTH{1'b0}};
     reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg  = {KEEP_WIDTH{1'b0}};
     reg                  temp_m_axis_tvalid_reg = 1'b0;
-    reg                  temp_m_axis_tvalid_next;
+    reg                  temp_m_axis_tvalid_next = 0;
     reg                  temp_m_axis_tlast_reg  = 1'b0;
     reg [ID_WIDTH-1:0]   temp_m_axis_tid_reg    = {ID_WIDTH{1'b0}};
     reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg  = {DEST_WIDTH{1'b0}};
     reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg  = {USER_WIDTH{1'b0}};
 
     // datapath control
-    reg store_axis_input_to_output;
-    reg store_axis_input_to_temp;
-    reg store_axis_temp_to_output;
+    reg store_axis_input_to_output = 0;
+    reg store_axis_input_to_temp = 0;
+    reg store_axis_temp_to_output = 0;
 
     assign s_axis_tready = s_axis_tready_reg;
 

diff --git a/benchmarks/fpga-debugging/axis-async-fifo-c4/tb.csv b/benchmarks/fpga-debugging/axis-async-fifo-c4/tb.csv
@@ -2,10 +2,10 @@ async_rst, input_axis_tdata, input_axis_tvalid, input_axis_tready, input_axis_tl
 1,  0,0,0,0,0,  0,0,0,0,0
 0,  1,0,0,0,0,  0,0,1,0,0
 0,  1,1,1,1,0,  0,0,1,0,0
-0,  2,1,x,1,0,  0,0,1,0,0
-0,  2,1,0,1,0,  0,0,1,0,0
 0,  2,1,1,1,0,  0,0,1,0,0
+0,  3,1,0,1,0,  0,0,1,0,0
 0,  3,1,1,1,0,  0,0,1,0,0
 0,  4,1,1,1,0,  0,0,1,0,0
 0,  5,1,1,1,0,  0,0,1,0,0
 0,  6,1,1,1,0,  1,1,1,1,0
+0,  7,1,1,1,0,  2,1,1,1,0
diff --git a/benchmarks/fpga-debugging/axis-async-fifo-c4/to_btor2.ys b/benchmarks/fpga-debugging/axis-async-fifo-c4/to_btor2.ys
@@ -0,0 +1,19 @@
+# read_sources
+read_verilog axis_async_fifo.v
+read_verilog axis_fifo_wrapper.v
+read_verilog axis_register.v
+
+hierarchy -top axis_fifo_wrapper
+
+# minimal btor
+proc -noopt
+
+# extra
+opt
+
+async2sync
+flatten
+dffunmap
+
+
+write_btor -x axis_async_fifo_wrapper.btor