bench: fix d9 source code

ekiwi · Jan 6, 2024 · cf63bea · cf63bea
1 parent 1e8b6b9
commit cf63bea
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/benchmarks/fpga-debugging/zipcpu-spi-c1-c3-d9/sdspi_bug_d9.v b/benchmarks/fpga-debugging/zipcpu-spi-c1-c3-d9/sdspi_bug_d9.v
@@ -654,6 +654,9 @@ module	sdspi(i_clk,
 			ll_fifo_addr <= ll_fifo_addr + 1;
 	end
 
+	reg	[(LGFIFOLN-1):0]	r_blklimit;
+	wire	[(LGFIFOLN+1):0]	w_blklimit;
+
 	//
 	// Look for that start token.  This will be present when reading from 
 	// the device into the FIFO.