Skip to content

Commit

Permalink
riscv: add mie unit tests
Browse files Browse the repository at this point in the history
Adds basic unit tests for the `mie` register.
  • Loading branch information
rmsyn committed Nov 5, 2024
1 parent d235173 commit 7b708fa
Showing 1 changed file with 17 additions and 0 deletions.
17 changes: 17 additions & 0 deletions riscv/src/register/mie.rs
Original file line number Diff line number Diff line change
Expand Up @@ -63,3 +63,20 @@ set_clear_csr!(
set_clear_csr!(
/// Machine External Interrupt Enable
, set_mext, clear_mext, 1 << 11);

#[cfg(test)]
mod tests {
use super::*;

#[test]
fn test_mie() {
let mut m = Mie::from_bits(0);

test_csr_field!(m, ssoft);
test_csr_field!(m, msoft);
test_csr_field!(m, stimer);
test_csr_field!(m, mtimer);
test_csr_field!(m, sext);
test_csr_field!(m, mext);
}
}

0 comments on commit 7b708fa

Please sign in to comment.