M85 firstbanner & logging #83372
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M85 firstbanner & logging #83372
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…et the command to build is west build -p always -b mps3_an547_tsv samples/hello_world when this target is made the image will be generated as zephyr.bin as well as we have turned on generation of zephyr.lst file to ensure we have debug symbols and disassemble code available The files changes are Kconfig.zephyr boards/arm/mps3/board.yml boards/arm/mps3/mps3_an547_tsv.dts boards/arm/mps3/mps3_an547_tsv.yaml boards/arm/mps3/mps3_an547_tsv_defconfig boards/deprecated.cmake
Altera UART JTAG driver in boards/arm/mps3/mps_an547_tsv.dts
This istest ready code but not verified yet.
… for jtag-uart. This will get the jtag-uart going, there is more work to be done on other IO addresses and we will make these changes are we bring up other IOs and test them.
… ITCM at 0x4000 The Zephyr RAM starts at 0x6000_8000
…tag-uart. This is ensuring the jtag-uart is being used for FPGA.
The UART addresses are correct for DV and FPGA environment and commented out unused peripherals and created TSV specific common DTSI.
Making changes to divide the SRAM in code and stack/heap into separate space on SRAM. This change finishes full execution of sample code in DV environment.
secure image, but the non secure image is broken in both fork as main in QEMU environment, so used mps3_an547 as a base for mps3_an547_tsv. Have mapped Flash as first section of 16K of SRAM, and the RAM for kernel is bottom 767K of SRAM, have mapped the other 1MB of SRAM0 and 2 MB of SRAM1 to SRAM and ISRAM respectively. | FLASH (16K) in SRAM0 | | 240K (Spare) in SRAM0 | | Kernel (767 K) in SRAM0 | | 1K (Spare) | | 1MB SRAM0 as SRAM | | 1MB SRAM1 as ISRAM | | 1MB SRAM1 as DDR | This is temporary arrangement to make progress. We will revist once we have jtag-uart and other FPGA functionality working.
Hello World in the DV environment.
address layout as follows | FLASH (32K) in SRAM0 | | Kernel (2016 K) in SRAM0 | | 1MB SRAM1 as ISRAM | | 1MB SRAM1 as DDR | Also fixed the addresses of ITCM and DTCM as 0x4000 and 0x20000000 which is what it is on the device and reflected the same in yaml.
as the user space applications are bigger, the hello_world_user is around 42K of code size. To accomodate this and future use cases made code area as 256K and adjusted Kernel Stack/Heap area to be 1792K as follows | FLASH (256K) in SRAM0 | | Kernel (1792 K) in SRAM0 | | 1MB SRAM1 as ISRAM | | 1MB SRAM1 as DDR | This change is tested with hello_world_user applications which starts a hello_world thread which is around 42K of code size.
as well as added changes to create zephyrstrp.hex without the first line so that it can be loaded as is on the sram.
generating new hex files.
the shell works as follows
uart:~$ help
Please press the <Tab> button to see all available commands.
You can also use the <Tab> button to prompt or auto-complete all commands or its subcommands.
You can try to call commands with <-h> or <--help> parameter for more information.
Shell supports following meta-keys:
Ctrl + (a key from: abcdefklnpuw)
Alt + (a key from: bf)
Please refer to shell documentation for more details.
Available commands:
clear : Clear screen.
device : Device commands
devmem : Read/write physical memory
Usage:
Read memory at address with optional width:
devmem address [width]
Write memory at address with mandatory width and value:
devmem address <width> <value>
help : Prints the help message.
history : Command history.
kernel : Kernel commands
rem : Ignore lines beginning with 'rem '
resize : Console gets terminal screen size or assumes default in case the
readout fails. It must be executed after each terminal width change
to ensure correct text display.
retval : Print return value of most recent command
shell : Useful, not Unix-like shell commands.
The command to use for beuild is as follows
"west build -p always -b mps3_an547_tsv samples/subsys/shell/devmem_load/ \
-- -DOVERLAY_CONFIG=prj_poll.conf"
to be used by all developers for FPGA and DV testing the build now generate IMAGE0_testfile.hex
… - skyp & CPUcore : m85 and modified file names accordingly
* TSI: board name changed -ek_tsi to tsi board name changed -comilance erros removed from some files Signed-off-by: Ganesh Kethamalla <[email protected]> * TSI Board: compliance errors removed and and board variant name changed -board variant name changed to m85 to cortex-m85 -white spaces and extra lines removed Signed-off-by: Ganesh Kethamalla <[email protected]> * TSI Board: old board file removed from directory -created tsi new directory, instead of using ek_tsi. that's removed old one. Signed-off-by: Ganesh Kethamalla <[email protected]> * added new cpu configuration adsp * Modified TXE address for DV environment testing * @FIR-13: Create a new target "west build -p always -b tsi/skyp/txe samples/hello_world/" and remove the old target "west build -p always -b tsi/mimx8ml8/adsp samples/hello_world/" there are still references to using mimx8m tool chain and drivers but we will revisit these later, I tried to make the change but gave up as it requires defining all of SOC structure will rely on Ganesh to address these items. * @FIR-13: Fix the lint and compliance warnings * @FIR-13: Fixed compliance warning * @FIR-13: Added tsi - Tsavorite Scalable Intelligence as a vendor * @FIR-13: Fixed the sorting issue of vendors list * removed unused symbol BOARD_TSI_MIMX8ML8_ADSP * Synced for new target tsi/skyp/m85 that removed the ek_ prefix * Removed white-spaces in main.c and Readme.rst * renamed folder boards/tsi/tsi to boards/tsi/skyp * Removed compilance check warnings --------- Signed-off-by: Ganesh Kethamalla <[email protected]> Co-authored-by: Dinesh Reddy <[email protected]> Co-authored-by: Ashish Trivedi <[email protected]> Co-authored-by: Meera Mankali <[email protected]>
1. for 4MB SRAM divided into different regions 2. JUART addresses starting from 0x85003000 instead of 0x95003000 3. Peripherals starting from 0x71000000 + 0x14000000 instead of 0x95001000
The G0208 SKYP branch has peripheral accesses of UART and SPI disabled Removing the peripheral block from the DTS file
Reverted changes which were done to MPS3 to build TSI targets
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