M85 firstbanner & logging

CMakeLists.txt

@@ -2020,6 +2020,48 @@ add_custom_command(
   COMMAND_EXPAND_LISTS
   )
 
+if(CONFIG_BUILD_OUTPUT_TSV_STRIPPED_HEX)
+# Add post_build_commands to post-process the final .hex file produced by
+# stripping first line of zephyr.hex
+find_package(Perl REQUIRED)
+set(MERGED_KERNEL_HEX_NAME merged.hex)
+set(BIN_2_HEX_OPTION --width=64)
+set(BIN2HEX scripts/build/bin2heximage)
+add_custom_command(
+    OUTPUT ${MERGED_KERNEL_HEX_NAME}
+    COMMAND rm -fr ${PROJECT_BINARY_NAME}/*.hex
+    COMMAND ${PERL_EXECUTABLE} ${ZEPHYR_BASE}/${BIN2HEX} ${PROJECT_BINARY_DIR}/${KERNEL_BIN_NAME} ${PROJECT_BINARY_DIR}/${KERNEL_HEX_NAME} ${BIN_2_HEX_OPTION}
+    DEPENDS ${logical_target_for_zephyr_elf}
+    )
+
+    add_custom_target(bin2hex ALL DEPENDS ${MERGED_KERNEL_HEX_NAME})
+    list(APPEND RUNNERS_DEPS bin2hex)
+    message(VERBOSE "Creating hex files: ${MERGED_KERNEL_HEX_NAME}")
+
+# Remove the 1st line of elf header from the zepher.hex file
+# and call the enw file as zephyrstrp.hex
+
+set(STRIPPED_KERNEL_HEX_NAME stripped.hex)
+set(STRIPPED_HEX_NAME zephyrstrp.hex)
+set(TAIL_EXECUTABLE /usr/bin/tail)
+set(HEAD_EXECUTABLE /usr/bin/head)
+set(TSVBOOTLOADER_NAME scripts/build/tsvbootloader.hex)
+set(TSVIMAGELOADER_NAME IMAGE0_testfile.hex)
+add_custom_command(
+	OUTPUT ${STRIPPED_KERNEL_HEX_NAME}
+	COMMAND ${TAIL_EXECUTABLE} -n +2 ${PROJECT_BINARY_DIR}/${KERNEL_HEX_NAME} >> ${PROJECT_BINARY_DIR}/${STRIPPED_HEX_NAME}
+	COMMAND ${HEAD_EXECUTABLE} -n +48 ${ZEPHYR_BASE}/${TSVBOOTLOADER_NAME} >> ${PROJECT_BINARY_DIR}/${TSVIMAGELOADER_NAME}
+	COMMAND ${HEAD_EXECUTABLE} -n +1 ${PROJECT_BINARY_DIR}/${STRIPPED_HEX_NAME} >> ${PROJECT_BINARY_DIR}/${TSVIMAGELOADER_NAME}
+	COMMAND ${TAIL_EXECUTABLE} -n +50 ${ZEPHYR_BASE}/${TSVBOOTLOADER_NAME} >> ${PROJECT_BINARY_DIR}/${TSVIMAGELOADER_NAME}
+	COMMAND ${TAIL_EXECUTABLE} -n +1 ${PROJECT_BINARY_DIR}/${STRIPPED_HEX_NAME} >> ${PROJECT_BINARY_DIR}/${TSVIMAGELOADER_NAME}
+	DEPENDS ${MERGED_KERNEL_HEX_NAME}
+    )
+
+    add_custom_target(strippedhex ALL DEPENDS ${STRIPPED_KERNEL_HEX_NAME})
+    list(APPEND RUNNERS_DEPS strippedhex)
+    message(VERBOSE "strippng hex files: ${STRIPPED_KERNEL_HEX_NAME}")
+endif()
+
 # To populate with hex files to merge, do the following:
 #  set_property(GLOBAL APPEND PROPERTY HEX_FILES_TO_MERGE ${my_local_list})
 # Note that the zephyr.hex file will not be included automatically.

Kconfig.zephyr

@@ -648,12 +648,13 @@ config OUTPUT_SYMBOLS
 
 config OUTPUT_DISASSEMBLY
 	bool "Create a disassembly file"
+	default y
 	help
 	  Create an .lst file with the assembly listing of the firmware.
 
 config OUTPUT_DISASSEMBLE_ALL
 	bool "Disassemble all sections with source. Fill zeros."
-	default n
+	default y
 	depends on OUTPUT_DISASSEMBLY
 	help
 	  The .lst file will contain complete disassembly of the firmware
@@ -707,6 +708,12 @@ config BUILD_OUTPUT_BIN
 	  Build a "raw" binary zephyr/zephyr.bin in the build directory.
 	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
 
+config BUILD_OUTPUT_TSV_STRIPPED_HEX
+        bool "Build a Stripped Hex file"
+        default n
+        help
+          Build a "raw" hex zephyr/zephyrstrp.hex in the build directory.
+
 config BUILD_OUTPUT_EFI
 	bool "Build as an EFI application"
 	default n

boards/tsi/skyp/Kconfig

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+# config BOARD_TSI
+# 	select QEMU_TARGET

boards/tsi/skyp/Kconfig.defconfig

@@ -0,0 +1,21 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_TSI
+
+# MPU-based null-pointer dereferencing detection cannot
+# be applied as the (0x0 - 0x400) is unmapped but QEMU
+# will still permit bus access.
+choice NULL_POINTER_EXCEPTION_DETECTION
+	bool
+	default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET
+endchoice
+
+if SERIAL
+
+config UART_INTERRUPT_DRIVEN
+	default n
+
+endif # SERIAL
+
+endif

boards/tsi/skyp/Kconfig.tsi

@@ -0,0 +1,7 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_TSI
+	select SOC_PART_NUMBER_MIMX8ML8DVNLZ
+	select SOC_SKYP_M85 if BOARD_TSI_SKYP_M85
+	select SOC_MIMX8ML8_ADSP if BOARD_TSI_SKYP_TXE

boards/tsi/skyp/board.yml

@@ -0,0 +1,10 @@
+board:
+  name: tsi
+  vendor: tsi
+  socs:
+  - name: skyp
+    variants:
+    - name: tensilica
+      cpucluster: txe
+    - name: cortex-m85
+      cpucluster: m85

boards/tsi/skyp/tsi_skyp_m85-common.dtsi

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019-2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ sysclk: system-clock {
+	compatible = "fixed-clock";
+	clock-frequency = <25000000>;
+	#clock-cells = <0>;
+};
+
+uart0: uart@14001000 {
+	compatible = "arm,cmsdk-uart";
+	reg = <0x14001000 0x1000>;
+	interrupts = <34 3 33 3>;
+	interrupt-names = "tx", "rx";
+	clocks = <&sysclk>;
+	current-speed = <115200>;
+};

boards/tsi/skyp/tsi_skyp_m85.dts

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2024 TSI
+ * Copyright 2022 Arm Limited and/or its affiliates <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm/armv8.1-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <mem.h>
+
+/ {
+	compatible = "arm,mps3-an547";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &jtag_uart;
+		zephyr,shell-uart = &jtag_uart;
+		zephyr,sram = &sram;
+		zephyr,flash = &sram0;
+	};
+
+	jtag_uart: uart@85003000 {
+		compatible = "altr,jtag-uart";
+		reg = <0x85003000 0x8>;
+		status = "enabled";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m85";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8.1m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	/* We utilize the secure addresses, if you subtract 0x10000000
+	 * you'll get the non-secure alias
+	 */
+	itcm: itcm@4000 {   /* alias @ 0x4000 */
+		compatible = "zephyr,memory-region";
+		reg = <0x4000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "ITCM";
+	};
+
+	sram0: sram0@60000000 {	/* alias @ 0x60000000 */
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_K(256)>;
+		zephyr,memory-region = "SRAM0";
+	};
+
+	sram: sram@60040000 {	/* alias @ 0x60040000 */
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x60040000 DT_SIZE_K(1792)>;
+		zephyr,memory-region = "SRAM";
+	};
+
+	dtcm: dtcm@20000000 {	/* alias @ 0x20000000 */
+		compatible = "zephyr,memory-region";
+		reg = <0x20000000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	isram: sram@60200000 {/* alias @ 0x60200000, lower 1MB of 2 MB SRAM1 */
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x60200000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "ISRAM";
+	};
+
+	/* Higher 1 MB of 2MB high SRAM */
+	sram1: memory@60300000 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region";
+		reg = <0x60300000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "SRAM1";
+	};
+
+	/*soc {
+		peripheral@71000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x71000000 0x1effffff>;
+
+			 #include "tsi_skyp_m85-common.dtsi"
+		};
+	};*/
+};
+
+&jtag_uart {
+	status = "okay";
+	current-speed = <9600>;
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};

boards/tsi/skyp/tsi_skyp_m85.yaml

@@ -0,0 +1,12 @@
+identifier: tsi/skyp/m85
+name: TSI sky-p
+type: mcu
+arch: arm
+ram: 1792
+flash: 256
+simulation: qemu
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+vendor: arm

boards/tsi/skyp/tsi_skyp_m85_defconfig

@@ -0,0 +1,18 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_RUNTIME_NMI=y
+CONFIG_ARM_TRUSTZONE_M=n
+CONFIG_ARM_MPU=y
+CONFIG_QEMU_ICOUNT_SHIFT=7
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+
+# Build a Secure firmware image
+CONFIG_TRUSTED_EXECUTION_SECURE=n
+
+# Build the zephyr.hex and zephyrstrp.hex for FPGA
+CONFIG_BUILD_OUTPUT_TSV_STRIPPED_HEX=y

boards/tsi/skyp/tsi_skyp_txe.dts

@@ -0,0 +1,47 @@
+/*
+ * Copyright 2021, 2023, 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_imx8m.dtsi>
+#include <nxp/nxp_imx/mimx8ml8dvnlz-pinctrl.dtsi>
+
+/ {
+	model = "NXP i.MX 8MPLUS Audio DSP";
+	compatible = "nxp";
+
+	chosen {
+		//zephyr,sram = &sram0;
+		zephyr,sram = &sram_txe;
+
+		zephyr,console = &uart4;
+		zephyr,shell-uart = &uart4;
+	};
+	sram_txe: memory@60040000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x60040000 DT_SIZE_K(512)>;
+	};
+};
+
+&pinctrl {
+	uart4_default: uart4_default {
+		group0 {
+			pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>,
+				<&iomuxc_uart4_txd_uart_tx_uart4_tx>;
+			bias-pull-up;
+			slew-rate = "slow";
+			drive-strength = "x1";
+		};
+	};
+};
+
+&uart4 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart4_default>;
+	pinctrl-names = "default";
+};

boards/tsi/skyp/tsi_skyp_txe.yaml

@@ -0,0 +1,16 @@
+identifier: tsi/skyp/txe
+name: TSI DSP
+type: mcu
+arch: xtensa
+toolchain:
+  - xcc
+  - xt-clang
+  - zephyr
+supported:
+  - uart
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - mcumgr
+vendor: nxp

boards/tsi/skyp/tsi_skyp_txe_defconfig

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# size of stack for initialization and main thread
+CONFIG_MAIN_STACK_SIZE=3072
+
+# enable logger
+CONFIG_LOG=y
+
+# no need for a "raw" binary zephyr/zephyr.bin in the build directory
+CONFIG_BUILD_OUTPUT_BIN=y
+CONFIG_BUILD_OUTPUT_HEX=y
+
+# enable uart driver
+CONFIG_SERIAL=y
+
+# clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# console (remote proc console by default)
+CONFIG_CONSOLE=y
+
+# uart console (overrides remote proc console)
+CONFIG_UART_CONSOLE=y
+
+# enable pin controller
+CONFIG_PINCTRL=y

dts/bindings/vendor-prefixes.txt

@@ -683,6 +683,7 @@ tronfy	Tronfy
 tronsmart	Tronsmart
 truly	Truly Semiconductors Limited
 tsd	Theobroma Systems Design und Consulting GmbH
+tsi	Tsavorite Scalable Intelligence
 tyan	Tyan Computer Corporation
 u-blox	u-blox
 u-boot	U-Boot bootloader