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Feature INCLUDE keyword (#224)
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* INCLUDE keyword for building fabric

* Include complete

* Add doc

* allow nested include entry

* formatting

* remove not needed print

* Update docs/source/fabric_definition.rst

Co-authored-by: Marcel Jung <[email protected]>

* Update docs/source/fabric_definition.rst

Co-authored-by: Marcel Jung <[email protected]>

* Apply suggestions from code review

Co-authored-by: Marcel Jung <[email protected]>

* More update

---------

Co-authored-by: King Lok Chung <[email protected]>
Co-authored-by: Marcel Jung <[email protected]>
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@KelvinChung2000 @IAmMarcelJung
3 people authored Aug 9, 2024
1 parent 73f57a0 commit 39d7b81
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Showing 19 changed files with 548 additions and 777 deletions.
1 change: 0 additions & 1 deletion FABulous/FABulous.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1283,7 +1283,6 @@ def do_gen_bitStream_binary(self, args):
f"{self.projectDir}/.FABulous/bitStreamSpec.bin",
f"{self.projectDir}/{parent}/{bitstream_file}",
]

try:
sp.run(runCmd, check=True)
except sp.CalledProcessError:
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6 changes: 3 additions & 3 deletions FABulous/fabric_cad/model_generation_npnr.py
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
from loguru import logger

from FABulous.fabric_definition.Fabric import Fabric
from FABulous.fabric_generator.utilities import parseList, parseMatrix
from FABulous.fabric_generator.file_parser import parseList, parseMatrix


def genNextpnrModel(fabric: Fabric):
Expand Down Expand Up @@ -43,14 +43,14 @@ def genNextpnrModel(fabric: Fabric):
if tile is None:
continue
pipStr.append(f"#Tile-internal pips on tile X{x}Y{y}:")
if tile.matrixDir.endswith(".csv"):
if tile.matrixDir.suffix == ".csv":
connection = parseMatrix(tile.matrixDir, tile.name)
for source, sinkList in connection.items():
for sink in sinkList:
pipStr.append(
f"X{x}Y{y},{sink},X{x}Y{y},{source},{8},{sink}.{source}"
)
elif tile.matrixDir.endswith(".list"):
elif tile.matrixDir.suffix == ".list":
connection = parseList(tile.matrixDir)
for sink, source in connection:
pipStr.append(
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9 changes: 5 additions & 4 deletions FABulous/fabric_definition/Bel.py
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
from dataclasses import dataclass, field
import pathlib
from FABulous.fabric_definition.define import IO


Expand All @@ -15,7 +16,7 @@ class Bel:
Attributes
----------
src : str
src : pathlib.Path
The source directory of the BEL given in the CSV file.
prefix : str
The prefix of the BEL given in the CSV file.
Expand Down Expand Up @@ -43,7 +44,7 @@ class Bel:
Indicates if ports are individually declared. Default is False.
"""

src: str
src: pathlib.Path
prefix: str
name: str
inputs: list[str]
Expand All @@ -59,7 +60,7 @@ class Bel:

def __init__(
self,
src: str,
src: pathlib.Path,
prefix: str,
internal,
external,
Expand All @@ -72,7 +73,7 @@ def __init__(
) -> None:
self.src = src
self.prefix = prefix
self.name = src.split("/")[-1].split(".")[0]
self.name = src.stem
self.inputs = [p for p, io in internal if io == IO.INPUT]
self.outputs = [p for p, io in internal if io == IO.OUTPUT]
self.externalInput = [p for p, io in external if io == IO.INPUT]
Expand Down
14 changes: 8 additions & 6 deletions FABulous/fabric_definition/Tile.py
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
from FABulous.fabric_definition.Port import Port
from FABulous.fabric_definition.Wire import Wire
from typing import Any
import pathlib


@dataclass
Expand All @@ -26,26 +27,27 @@ class Tile:
Whether the tile has a userCLK port. Default is False.
wireList : list[Wire]
The list of wires of the tile
filePath : str
The path of the matrix file
tileDir : str
The path to the tile folder
"""

name: str
portsInfo: list[Port]
bels: list[Bel]
matrixDir: str
matrixDir: pathlib.Path
globalConfigBits: int = 0
withUserCLK: bool = False
wireList: list[Wire] = field(default_factory=list)
filePath: str = "."
tileDir: pathlib.Path = pathlib.Path(".")
partOfSuperTile = False

def __init__(
self,
name: str,
ports: list[Port],
bels: list[Bel],
matrixDir: str,
tileDir: pathlib.Path,
matrixDir: pathlib.Path,
userCLK: bool,
configBit: int = 0,
) -> None:
Expand All @@ -56,7 +58,7 @@ def __init__(
self.withUserCLK = userCLK
self.globalConfigBits = configBit
self.wireList = []
self.filePath = os.path.split(matrixDir)[0]
self.tileDir = tileDir

for b in self.bels:
self.globalConfigBits += b.configBit
Expand Down
43 changes: 1 addition & 42 deletions FABulous/fabric_files/FABulous_project_template_verilog/Tile/DSP/DSP_bot/DSP_bot.csv
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Original file line number Diff line number Diff line change
@@ -1,49 +1,8 @@
TILE,DSP_bot,,,,,,,,,,,,,,,,,
#direction,source_name,X-offset,Y-offset,destination_name,wires,,,,,,,,,,,,,
NORTH,N1BEG,0,-1,N1END,4,,,,,,,,,,,,,
NORTH,N2BEG,0,-1,N2MID,8,,,,,,,,,,,,,
NORTH,N2BEGb,0,-1,N2END,8,,,,,,,,,,,,,
NORTH,N4BEG,0,-4,N4END,4,,,,,,,,,,,,,
NORTH,NN4BEG,0,-4,NN4END,4,,,,,,,,,,,,,
INCLUDE,../../include/Base.csv
NORTH,bot2top,0,-1,NULL,10,,,,,,,,,,,,,
EAST,E1BEG,1,0,E1END,4,,,,,,,,,,,,,
EAST,E2BEG,1,0,E2MID,8,,,,,,,,,,,,,
EAST,E2BEGb,1,0,E2END,8,,,,,,,,,,,,,
EAST,EE4BEG,4,0,EE4END,4,,,,,,,,,,,,,
EAST,E6BEG,6,0,E6END,2,,,,,,,,,,,,,
SOUTH,S1BEG,0,1,S1END,4,,,,,,,,,,,,,
SOUTH,S2BEG,0,1,S2MID,8,,,,,,,,,,,,,
SOUTH,S2BEGb,0,1,S2END,8,,,,,,,,,,,,,
SOUTH,S4BEG,0,4,S4END,4,,,,,,,,,,,,,
SOUTH,SS4BEG,0,4,SS4END,4,,,,,,,,,,,,,
SOUTH,NULL,0,1,top2bot,18,,,,,,,,,,,,,
WEST,W1BEG,-1,0,W1END,4,,,,,,,,,,,,,
WEST,W2BEG,-1,0,W2MID,8,,,,,,,,,,,,,
WEST,W2BEGb,-1,0,W2END,8,,,,,,,,,,,,,
WEST,WW4BEG,-4,0,WW4END,4,,,,,,,,,,,,,
WEST,W6BEG,-6,0,W6END,2,,,,,,,,,,,,,
JUMP,J2MID_ABa_BEG,0,0,J2MID_ABa_END,4,,,,,,,,,,,,,
JUMP,J2MID_CDa_BEG,0,0,J2MID_CDa_END,4,,,,,,,,,,,,,
JUMP,J2MID_EFa_BEG,0,0,J2MID_EFa_END,4,,,,,,,,,,,,,
JUMP,J2MID_GHa_BEG,0,0,J2MID_GHa_END,4,,,,,,,,,,,,,
JUMP,J2MID_ABb_BEG,0,0,J2MID_ABb_END,4,,,,,,,,,,,,,
JUMP,J2MID_CDb_BEG,0,0,J2MID_CDb_END,4,,,,,,,,,,,,,
JUMP,J2MID_EFb_BEG,0,0,J2MID_EFb_END,4,,,,,,,,,,,,,
JUMP,J2MID_GHb_BEG,0,0,J2MID_GHb_END,4,,,,,,,,,,,,,
JUMP,J2END_AB_BEG,0,0,J2END_AB_END,4,,,,,,,,,,,,,
JUMP,J2END_CD_BEG,0,0,J2END_CD_END,4,,,,,,,,,,,,,
JUMP,J2END_EF_BEG,0,0,J2END_EF_END,4,,,,,,,,,,,,,
JUMP,J2END_GH_BEG,0,0,J2END_GH_END,4,,,,,,,,,,,,,
JUMP,JN2BEG,0,0,JN2END,8,,,,,,,,,,,,,
JUMP,JE2BEG,0,0,JE2END,8,,,,,,,,,,,,,
JUMP,JS2BEG,0,0,JS2END,8,,,,,,,,,,,,,
JUMP,JW2BEG,0,0,JW2END,8,,,,,,,,,,,,,
JUMP,J_l_AB_BEG,0,0,J_l_AB_END,4,,,,,,,,,,,,,
JUMP,J_l_CD_BEG,0,0,J_l_CD_END,4,,,,,,,,,,,,,
JUMP,J_l_EF_BEG,0,0,J_l_EF_END,4,,,,,,,,,,,,,
JUMP,J_l_GH_BEG,0,0,J_l_GH_END,4,,,,,,,,,,,,,
JUMP,NULL,0,0,GND,1,,,,,,,,,,,,,
JUMP,NULL,0,0,VCC,1,,,,,,,,,,,,,
BEL,./MULADD.v,,,,,,,,,,,,,,,,,
MATRIX,./DSP_bot_switch_matrix.list,,,,,,,,,,,,,,,,,
EndTILE,,,,,,,,,,,,,,,,,,
76 changes: 2 additions & 74 deletions ...abric_files/FABulous_project_template_verilog/Tile/DSP/DSP_bot/DSP_bot_switch_matrix.list
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Original file line number Diff line number Diff line change
@@ -1,77 +1,5 @@
# LUT4AB
# double with MID cascade : [N,E,S,W]2BEG --- [N,E,S,W]2MID -> [N,E,S,W]2BEGb --- [N,E,S,W]2END (just routing)
[N|E|S|W]2BEGb[0|1|2|3|4|5|6|7],[N|E|S|W]2MID[0|1|2|3|4|5|6|7]

# shared double MID jump wires
J2MID_ABa_BEG[0|0|0|0],[JN2END3|N2MID6|S2MID6|W2MID6]
J2MID_ABa_BEG[1|1|1|1],[E2MID2|JE2END3|S2MID2|W2MID2]
J2MID_ABa_BEG[2|2|2|2],[E2MID4|N2MID4|JS2END3|W2MID4]
J2MID_ABa_BEG[3|3|3|3],[E2MID0|N2MID0|S2MID0|JW2END3]
J2MID_CDa_BEG[0|0|0|0],[E2MID6|JN2END4|S2MID6|W2MID6]
J2MID_CDa_BEG[1|1|1|1],[E2MID2|N2MID2|JE2END4|W2MID2]
J2MID_CDa_BEG[2|2|2|2],[E2MID4|N2MID4|S2MID4|JS2END4]
J2MID_CDa_BEG[3|3|3|3],[JW2END4|N2MID0|S2MID0|W2MID0]
J2MID_EFa_BEG[0|0|0|0],[E2MID6|N2MID6|JN2END5|W2MID6]
J2MID_EFa_BEG[1|1|1|1],[E2MID2|N2MID2|S2MID2|JE2END5]
J2MID_EFa_BEG[2|2|2|2],[JS2END5|N2MID4|S2MID4|W2MID4]
J2MID_EFa_BEG[3|3|3|3],[E2MID0|JW2END5|S2MID0|W2MID0]
J2MID_GHa_BEG[0|0|0|0],[E2MID6|N2MID6|S2MID6|JN2END6]
J2MID_GHa_BEG[1|1|1|1],[JE2END6|N2MID2|S2MID2|W2MID2]
J2MID_GHa_BEG[2|2|2|2],[E2MID4|JS2END6|S2MID4|W2MID4]
J2MID_GHa_BEG[3|3|3|3],[E2MID0|N2MID0|JW2END6|W2MID0]

J2MID_ABb_BEG[0|0|0|0],[E2MID7|N2MID7|S2MID7|W2MID7]
J2MID_ABb_BEG[1|1|1|1],[E2MID3|N2MID3|S2MID3|W2MID3]
J2MID_ABb_BEG[2|2|2|2],[E2MID5|N2MID5|S2MID5|W2MID5]
J2MID_ABb_BEG[3|3|3|3],[E2MID1|N2MID1|S2MID1|W2MID1]
J2MID_CDb_BEG[0|0|0|0],[E2MID7|N2MID7|S2MID7|W2MID7]
J2MID_CDb_BEG[1|1|1|1],[E2MID3|N2MID3|S2MID3|W2MID3]
J2MID_CDb_BEG[2|2|2|2],[E2MID5|N2MID5|S2MID5|W2MID5]
J2MID_CDb_BEG[3|3|3|3],[E2MID1|N2MID1|S2MID1|W2MID1]
J2MID_EFb_BEG[0|0|0|0],[E2MID7|N2MID7|S2MID7|W2MID7]
J2MID_EFb_BEG[1|1|1|1],[E2MID3|N2MID3|S2MID3|W2MID3]
J2MID_EFb_BEG[2|2|2|2],[E2MID5|N2MID5|S2MID5|W2MID5]
J2MID_EFb_BEG[3|3|3|3],[E2MID1|N2MID1|S2MID1|W2MID1]
J2MID_GHb_BEG[0|0|0|0],[E2MID7|N2MID7|S2MID7|W2MID7]
J2MID_GHb_BEG[1|1|1|1],[E2MID3|N2MID3|S2MID3|W2MID3]
J2MID_GHb_BEG[2|2|2|2],[E2MID5|N2MID5|S2MID5|W2MID5]
J2MID_GHb_BEG[3|3|3|3],[E2MID1|N2MID1|S2MID1|W2MID1]

# shared double END jump wires
J2END_AB_BEG[0|0|0|0],[E2END6|N2END6|SS4END3|W2END6]
J2END_AB_BEG[1|1|1|1],[E2END2|NN4END0|S2END2|W2END2]
J2END_AB_BEG[2|2|2|2],[EE4END0|N2END4|S2END4|W2END4]
J2END_AB_BEG[3|3|3|3],[E2END0|N2END0|S2END0|WW4END3]
J2END_CD_BEG[0|0|0|0],[E2END6|NN4END3|S2END6|W2END6]
J2END_CD_BEG[1|1|1|1],[E2END2|N2END2|S2END2|WW4END2]
J2END_CD_BEG[2|2|2|2],[E2END4|N2END4|SS4END2|W2END4]
J2END_CD_BEG[3|3|3|3],[EE4END1|N2END0|S2END0|W2END0]
J2END_EF_BEG[0|0|0|0],[EE4END2|N2END7|S2END7|W2END7]
J2END_EF_BEG[1|1|1|1],[E2END3|N2END3|S2END3|WW4END1]
J2END_EF_BEG[2|2|2|2],[E2END5|N2END5|SS4END1|W2END5]
J2END_EF_BEG[3|3|3|3],[E2END1|NN4END2|S2END1|W2END1]
J2END_GH_BEG[0|0|0|0],[E2END7|N2END7|S2END7|WW4END0]
J2END_GH_BEG[1|1|1|1],[E2END3|N2END3|SS4END0|W2END3]
J2END_GH_BEG[2|2|2|2],[E2END5|NN4END1|S2END5|W2END5]
J2END_GH_BEG[3|3|3|3],[EE4END3|N2END1|S2END1|W2END1]

# shared double END jump wires I shared that with the flop outputs
J_l_AB_BEG[0|0|0|0],[JN2END1|NN4END3|S4END3|WW4END0]
J_l_AB_BEG[1|1|1|1],[EE4END2|JE2END1|S4END2|W2END7]
J_l_AB_BEG[2|2|2|2],[E6END1|N4END1|JS2END1|W6END1]
J_l_AB_BEG[3|3|3|3],[E6END0|N4END0|S4END0|JW2END1]
J_l_CD_BEG[0|0|0|0],[E2END3|JN2END2|SS4END3|WW4END2]
J_l_CD_BEG[1|1|1|1],[E2END2|N4END2|JE2END2|W2END7]
J_l_CD_BEG[2|2|2|2],[EE4END1|NN4END1|S4END1|JS2END2]
J_l_CD_BEG[3|3|3|3],[JW2END2|N4END0|SS4END0|W6END0]
J_l_EF_BEG[0|0|0|0],[E2END3|N4END3|JN2END3|W2END3]
J_l_EF_BEG[1|1|1|1],[E2END2|NN4END2|S4END2|JE2END3]
J_l_EF_BEG[2|2|2|2],[JS2END3|N4END1|SS4END1|W2END4]
J_l_EF_BEG[3|3|3|3],[EE4END3|JW2END3|S4END0|WW4END1]
J_l_GH_BEG[0|0|0|0],[EE4END0|N4END3|S4END3|JN2END4]
J_l_GH_BEG[1|1|1|1],[JE2END4|N4END2|SS4END2|W2END2]
J_l_GH_BEG[2|2|2|2],[E6END1|JS2END4|S4END1|WW4END3]
J_l_GH_BEG[3|3|3|3],[E6END0|NN4END0|JW2END4|W2END0]
# DSP_bot
INCLUDE, ../../include/Base.list

# operand A LSBs
A[0|0|0|0],[J2MID_ABa_END0|J2MID_ABb_END0|J2END_AB_END0|J_l_AB_END0]
Expand Down
41 changes: 1 addition & 40 deletions FABulous/fabric_files/FABulous_project_template_verilog/Tile/DSP/DSP_top/DSP_top.csv
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Original file line number Diff line number Diff line change
@@ -1,46 +1,7 @@
TILE,DSP_top,,,,,,,,,,,,,,,,,
#direction,source_name,X-offset,Y-offset,destination_name,wires,,,,,,,,,,,,,
NORTH,N1BEG,0,-1,N1END,4,,,,,,,,,,,,,
NORTH,N2BEG,0,-1,N2MID,8,,,,,,,,,,,,,
NORTH,N2BEGb,0,-1,N2END,8,,,,,,,,,,,,,
NORTH,N4BEG,0,-4,N4END,4,,,,,,,,,,,,,
NORTH,NN4BEG,0,-4,NN4END,4,,,,,,,,,,,,,
INCLUDE,../../include/Base.csv
NORTH,NULL,0,-1,bot2top,10,,,,,,,,,,,,,
EAST,E1BEG,1,0,E1END,4,,,,,,,,,,,,,
EAST,E2BEG,1,0,E2MID,8,,,,,,,,,,,,,
EAST,E2BEGb,1,0,E2END,8,,,,,,,,,,,,,
EAST,EE4BEG,4,0,EE4END,4,,,,,,,,,,,,,
EAST,E6BEG,6,0,E6END,2,,,,,,,,,,,,,
SOUTH,S1BEG,0,1,S1END,4,,,,,,,,,,,,,
SOUTH,S2BEG,0,1,S2MID,8,,,,,,,,,,,,,
SOUTH,S2BEGb,0,1,S2END,8,,,,,,,,,,,,,
SOUTH,S4BEG,0,4,S4END,4,,,,,,,,,,,,,
SOUTH,SS4BEG,0,4,SS4END,4,,,,,,,,,,,,,
SOUTH,top2bot,0,1,NULL,18,,,,,,,,,,,,,
WEST,W1BEG,-1,0,W1END,4,,,,,,,,,,,,,
WEST,W2BEG,-1,0,W2MID,8,,,,,,,,,,,,,
WEST,W2BEGb,-1,0,W2END,8,,,,,,,,,,,,,
WEST,WW4BEG,-4,0,WW4END,4,,,,,,,,,,,,,
WEST,W6BEG,-6,0,W6END,2,,,,,,,,,,,,,
JUMP,J2MID_ABa_BEG,0,0,J2MID_ABa_END,4,,,,,,,,,,,,,
JUMP,J2MID_CDa_BEG,0,0,J2MID_CDa_END,4,,,,,,,,,,,,,
JUMP,J2MID_EFa_BEG,0,0,J2MID_EFa_END,4,,,,,,,,,,,,,
JUMP,J2MID_GHa_BEG,0,0,J2MID_GHa_END,4,,,,,,,,,,,,,
JUMP,J2MID_ABb_BEG,0,0,J2MID_ABb_END,4,,,,,,,,,,,,,
JUMP,J2MID_CDb_BEG,0,0,J2MID_CDb_END,4,,,,,,,,,,,,,
JUMP,J2MID_EFb_BEG,0,0,J2MID_EFb_END,4,,,,,,,,,,,,,
JUMP,J2MID_GHb_BEG,0,0,J2MID_GHb_END,4,,,,,,,,,,,,,
JUMP,J2END_AB_BEG,0,0,J2END_AB_END,4,,,,,,,,,,,,,
JUMP,J2END_CD_BEG,0,0,J2END_CD_END,4,,,,,,,,,,,,,
JUMP,J2END_EF_BEG,0,0,J2END_EF_END,4,,,,,,,,,,,,,
JUMP,J2END_GH_BEG,0,0,J2END_GH_END,4,,,,,,,,,,,,,
JUMP,JN2BEG,0,0,JN2END,8,,,,,,,,,,,,,
JUMP,JE2BEG,0,0,JE2END,8,,,,,,,,,,,,,
JUMP,JS2BEG,0,0,JS2END,8,,,,,,,,,,,,,
JUMP,JW2BEG,0,0,JW2END,8,,,,,,,,,,,,,
JUMP,J_l_AB_BEG,0,0,J_l_AB_END,4,,,,,,,,,,,,,
JUMP,J_l_CD_BEG,0,0,J_l_CD_END,4,,,,,,,,,,,,,
JUMP,J_l_EF_BEG,0,0,J_l_EF_END,4,,,,,,,,,,,,,
JUMP,J_l_GH_BEG,0,0,J_l_GH_END,4,,,,,,,,,,,,,
MATRIX,./DSP_top_switch_matrix.list,,,,,,,,,,,,,,,,,
EndTILE,,,,,,,,,,,,,,,,,,
80 changes: 2 additions & 78 deletions ...abric_files/FABulous_project_template_verilog/Tile/DSP/DSP_top/DSP_top_switch_matrix.list
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Original file line number Diff line number Diff line change
@@ -1,81 +1,5 @@
# LUT4AB
# double with MID cascade : [N,E,S,W]2BEG --- [N,E,S,W]2MID -> [N,E,S,W]2BEGb --- [N,E,S,W]2END (just routing)
[N|E|S|W]2BEGb[0|1|2|3|4|5|6|7],[N|E|S|W]2MID[0|1|2|3|4|5|6|7]

############## LUT Inputs ##############
############## LUT Inputs ##############
############## LUT Inputs ##############

# shared double MID jump wires
J2MID_ABa_BEG[0|0|0|0],[JN2END3|N2MID6|S2MID6|W2MID6]
J2MID_ABa_BEG[1|1|1|1],[E2MID2|JE2END3|S2MID2|W2MID2]
J2MID_ABa_BEG[2|2|2|2],[E2MID4|N2MID4|JS2END3|W2MID4]
J2MID_ABa_BEG[3|3|3|3],[E2MID0|N2MID0|S2MID0|JW2END3]
J2MID_CDa_BEG[0|0|0|0],[E2MID6|JN2END4|S2MID6|W2MID6]
J2MID_CDa_BEG[1|1|1|1],[E2MID2|N2MID2|JE2END4|W2MID2]
J2MID_CDa_BEG[2|2|2|2],[E2MID4|N2MID4|S2MID4|JS2END4]
J2MID_CDa_BEG[3|3|3|3],[JW2END4|N2MID0|S2MID0|W2MID0]
J2MID_EFa_BEG[0|0|0|0],[E2MID6|N2MID6|JN2END5|W2MID6]
J2MID_EFa_BEG[1|1|1|1],[E2MID2|N2MID2|S2MID2|JE2END5]
J2MID_EFa_BEG[2|2|2|2],[JS2END5|N2MID4|S2MID4|W2MID4]
J2MID_EFa_BEG[3|3|3|3],[E2MID0|JW2END5|S2MID0|W2MID0]
J2MID_GHa_BEG[0|0|0|0],[E2MID6|N2MID6|S2MID6|JN2END6]
J2MID_GHa_BEG[1|1|1|1],[JE2END6|N2MID2|S2MID2|W2MID2]
J2MID_GHa_BEG[2|2|2|2],[E2MID4|JS2END6|S2MID4|W2MID4]
J2MID_GHa_BEG[3|3|3|3],[E2MID0|N2MID0|JW2END6|W2MID0]

J2MID_ABb_BEG[0|0|0|0],[E2MID7|N2MID7|S2MID7|W2MID7]
J2MID_ABb_BEG[1|1|1|1],[E2MID3|N2MID3|S2MID3|W2MID3]
J2MID_ABb_BEG[2|2|2|2],[E2MID5|N2MID5|S2MID5|W2MID5]
J2MID_ABb_BEG[3|3|3|3],[E2MID1|N2MID1|S2MID1|W2MID1]
J2MID_CDb_BEG[0|0|0|0],[E2MID7|N2MID7|S2MID7|W2MID7]
J2MID_CDb_BEG[1|1|1|1],[E2MID3|N2MID3|S2MID3|W2MID3]
J2MID_CDb_BEG[2|2|2|2],[E2MID5|N2MID5|S2MID5|W2MID5]
J2MID_CDb_BEG[3|3|3|3],[E2MID1|N2MID1|S2MID1|W2MID1]
J2MID_EFb_BEG[0|0|0|0],[E2MID7|N2MID7|S2MID7|W2MID7]
J2MID_EFb_BEG[1|1|1|1],[E2MID3|N2MID3|S2MID3|W2MID3]
J2MID_EFb_BEG[2|2|2|2],[E2MID5|N2MID5|S2MID5|W2MID5]
J2MID_EFb_BEG[3|3|3|3],[E2MID1|N2MID1|S2MID1|W2MID1]
J2MID_GHb_BEG[0|0|0|0],[E2MID7|N2MID7|S2MID7|W2MID7]
J2MID_GHb_BEG[1|1|1|1],[E2MID3|N2MID3|S2MID3|W2MID3]
J2MID_GHb_BEG[2|2|2|2],[E2MID5|N2MID5|S2MID5|W2MID5]
J2MID_GHb_BEG[3|3|3|3],[E2MID1|N2MID1|S2MID1|W2MID1]

# shared double END jump wires
J2END_AB_BEG[0|0|0|0],[E2END6|N2END6|SS4END3|W2END6]
J2END_AB_BEG[1|1|1|1],[E2END2|NN4END0|S2END2|W2END2]
J2END_AB_BEG[2|2|2|2],[EE4END0|N2END4|S2END4|W2END4]
J2END_AB_BEG[3|3|3|3],[E2END0|N2END0|S2END0|WW4END3]
J2END_CD_BEG[0|0|0|0],[E2END6|NN4END3|S2END6|W2END6]
J2END_CD_BEG[1|1|1|1],[E2END2|N2END2|S2END2|WW4END2]
J2END_CD_BEG[2|2|2|2],[E2END4|N2END4|SS4END2|W2END4]
J2END_CD_BEG[3|3|3|3],[EE4END1|N2END0|S2END0|W2END0]
J2END_EF_BEG[0|0|0|0],[EE4END2|N2END7|S2END7|W2END7]
J2END_EF_BEG[1|1|1|1],[E2END3|N2END3|S2END3|WW4END1]
J2END_EF_BEG[2|2|2|2],[E2END5|N2END5|SS4END1|W2END5]
J2END_EF_BEG[3|3|3|3],[E2END1|NN4END2|S2END1|W2END1]
J2END_GH_BEG[0|0|0|0],[E2END7|N2END7|S2END7|WW4END0]
J2END_GH_BEG[1|1|1|1],[E2END3|N2END3|SS4END0|W2END3]
J2END_GH_BEG[2|2|2|2],[E2END5|NN4END1|S2END5|W2END5]
J2END_GH_BEG[3|3|3|3],[EE4END3|N2END1|S2END1|W2END1]

# shared double END jump wires I shared that with the flop outputs
J_l_AB_BEG[0|0|0|0],[JN2END1|NN4END3|S4END3|WW4END0]
J_l_AB_BEG[1|1|1|1],[EE4END2|JE2END1|S4END2|W2END7]
J_l_AB_BEG[2|2|2|2],[E6END1|N4END1|JS2END1|W6END1]
J_l_AB_BEG[3|3|3|3],[E6END0|N4END0|S4END0|JW2END1]
J_l_CD_BEG[0|0|0|0],[E2END3|JN2END2|SS4END3|WW4END2]
J_l_CD_BEG[1|1|1|1],[E2END2|N4END2|JE2END2|W2END7]
J_l_CD_BEG[2|2|2|2],[EE4END1|NN4END1|S4END1|JS2END2]
J_l_CD_BEG[3|3|3|3],[JW2END2|N4END0|SS4END0|W6END0]
J_l_EF_BEG[0|0|0|0],[E2END3|N4END3|JN2END3|W2END3]
J_l_EF_BEG[1|1|1|1],[E2END2|NN4END2|S4END2|JE2END3]
J_l_EF_BEG[2|2|2|2],[JS2END3|N4END1|SS4END1|W2END4]
J_l_EF_BEG[3|3|3|3],[EE4END3|JW2END3|S4END0|WW4END1]
J_l_GH_BEG[0|0|0|0],[EE4END0|N4END3|S4END3|JN2END4]
J_l_GH_BEG[1|1|1|1],[JE2END4|N4END2|SS4END2|W2END2]
J_l_GH_BEG[2|2|2|2],[E6END1|JS2END4|S4END1|WW4END3]
J_l_GH_BEG[3|3|3|3],[E6END0|NN4END0|JW2END4|W2END0]
# DSP_top
INCLUDE, ../../include/Base.list

# operand A MSBs
top2bot[0|0|0|0],[J2MID_ABa_END0|J2MID_ABb_END0|J2END_AB_END0|J_l_AB_END0]
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